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1. 发明公开

EP3350697A1 OUT OF ORDER COMMIT 审中-公开
公开(公告)号：EP3350697A1
公开(公告)日：2018-07-25
申请号：EP16770614.2
申请日：2016-09-12
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

2. 发明公开

EP3350690A1 IMPLICIT PROGRAM ORDER 有权转让
公开(公告)号：EP3350690A1
公开(公告)日：2018-07-25
申请号：EP16775908.3
申请日：2016-09-13
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

3. 发明公开

EP3350684A1 SEGMENTED INSTRUCTION BLOCK 审中-公开
公开(公告)号：EP3350684A1
公开(公告)日：2018-07-25
申请号：EP16775909.1
申请日：2016-09-13
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

4. 发明公开

EP3345088A1 DYNAMIC GENERATION OF NULL INSTRUCTIONS 有权转让
公开(公告)号：EP3345088A1
公开(公告)日：2018-07-11
申请号：EP16775911.7
申请日：2016-09-13
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F9/38 , G06F9/30 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

5. 发明公开

EP3022657A1 TECHNIQUES FOR CONTROLLING USE OF LOCKS 审中-公开
标题翻译： TECHNIKEN ZUR STEUERUNG DER VERWENDUNG VONSCHLÖSSERN
公开(公告)号：EP3022657A1
公开(公告)日：2016-05-25
申请号：EP13889446.4
申请日：2013-07-15
申请人： Intel Corporation
发明人： BAN, Khun , CHOW, Kingsum , AUNDHE, Shirish , VISWANATHAN, Sandhya
IPC分类号： G06F15/16
CPC分类号： G06F9/52 , G06F8/70 , G06F9/30076 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/528
摘要： Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于控制通过同时执行的代码部分来调节对共享资源的访问的锁的使用的技术。用于控制资源锁定的装置包括处理器组件，历史分析器，用于由处理器组件执行以用锁定标记来分析代替第一代码代码的锁定指令的至少一个结果，以允许处理器组件推测性地执行代码的第二实例，以及用于由处理器组件执行的锁定组件，以基于至少一个结果的分析，用于访问资源的代码的第一和第二实例来代替具有锁定标记的锁定指令;以及锁定指令，请求对该资源的访问锁定到第一个代码。描述和要求保护其他实施例。

6. 发明公开

EP3011465A1 SOFTWARE POLLING ELISION WITH RESTRICTED TRANSACTIONAL MEMORY 审中-公开
标题翻译：软件错误MITBESCHRÄNKTEMTRANSAKTIONSSPEICHER
公开(公告)号：EP3011465A1
公开(公告)日：2016-04-27
申请号：EP13887330.2
申请日：2013-06-18
申请人： Intel Corporation
发明人： ZHU, Lejun
IPC分类号： G06F15/163
CPC分类号： G06F9/3009 , G06F9/3004 , G06F9/44552 , G06F9/44557 , G06F9/467 , G06F9/528
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for software polling elision with restricted transactional memory. The device may include a restricted transactional memory (RTM) processor configured to monitor a region associated with a transaction and to enable an abort of the transaction, wherein the abort nullifies modifications to the region, the modifications associated with processing within the transaction prior to the abort. The device may also include a code module configured to: produce a first request; send the first request to an external processing entity; enter the transaction; produce a second request; commit the transaction in response to a completion indication from the external processing entity; and abort the transaction in response to a non-completion indication from the external entity. Software polling elision avoids the latency, and efficiency can be increased.
摘要翻译：通常，本公开提供了用于具有受限事务存储器的软件轮询检测的系统，设备，方法和计算机可读介质。该设备可以包括受限制的事务存储器（RTM）处理器，其被配置为监视与事务相关联的区域并且使得能够中止该事务，其中中止使对该区域的修改无效，该修改与该事务之前的处理相关联中止。所述设备还可以包括代码模块，所述代码模块被配置为：产生第一请求; 向外部处理实体发送第一个请求; 进入交易; 产生第二个请求; 响应来自外部处理实体的完成指示提交交易; 并且响应来自外部实体的非完成指示中止该事务。

7. 发明公开

EP2862084A1 A METHOD AND SYSTEM FOR IMPLEMENTING RECOVERY FROM SPECULATIVE FORWARDING MISS-PREDICTIONS/ERRORS RESULTING FROM LOAD STORE REORDERING AND OPTIMIZATION 审中-公开
标题翻译：方法和系统实现恢复遗漏对预测/错误引起的重排及存放费用的优化投机和传输
公开(公告)号：EP2862084A1
公开(公告)日：2015-04-22
申请号：EP13803753.6
申请日：2013-06-13
申请人： Soft Machines, Inc.
发明人： ABDALLAH, Mohammad
IPC分类号： G06F12/00
CPC分类号： G06F9/528 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/30185 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3855 , G06F12/0831
摘要： A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier.
摘要翻译：一种用于在乱序处理器从存储指令转发数据到对应的加载指令的方法。该方法包括访问到的指令输入序列; 重排与分派和执行处理器资源在雅舞蹈的说明; 确保以便机器最近早些时候存储到相应的负载，以确定开采，如果上述商店具有实际年龄，但表示相应的负载不必实际年龄，然后说店是比所述相应的负载早些时候; 说，如果相应的负载有实际年龄，但表示店内没有实际年龄那么相应的所述负载早于上述商店; 如果既不所述相应的加载或存储。所述得的实际年龄，然后虚拟标识符表被用于确定哪个是早些时候; 如果双方都表示相应的加载和存储有说实际年龄，则实际年龄来确定性矿所有这一切早。

8. 发明公开

EP1593038A1 METHOD AND APPARATUS FOR AVOIDING LOCKS BY SPECULATIVELY EXECUTING CRITICAL SECTIONS 审中-公开
标题翻译：方法和设备预防堵塞BY推测执行关键部件
公开(公告)号：EP1593038A1
公开(公告)日：2005-11-09
申请号：EP04706986.9
申请日：2004-01-30
申请人： SUN MICROSYSTEMS, INC.
发明人： CHAUDHRY, Shaildender , TREMBLAY, Marc , JACOBSON, Quinn, A.
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/528 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

9. 发明公开

EP1133725A1 A JOB-PARALLEL PROCESSOR 有权
标题翻译：在服务网络的并行作业处理系统
公开(公告)号：EP1133725A1
公开(公告)日：2001-09-19
申请号：EP99972320.8
申请日：1999-11-12
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： HOLMBERG, Per, Anders , KLING, Lars-Örjan , JOHNSON, Sten, Edward , EGELAND, Terje
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3857 , G06F9/528
摘要： The invention generally relates to a processor developed for a service network that provides various services to a plurality of users connected to the network. The processor (30; 50) comprises a job queue (52) with a number of storage positions for storing job signals corresponding to jobs that form part of substantially independent services requested by the users of the network, and a plurality of parallel processing units (54) which independently process job signals from different storage positions of the job queue (52) to execute corresponding jobs in parallel. As a number of jobs are executed speculatively, a unit (56) for checking for possible dependencies between the executed jobs is incorporated into the processor. If a dependency is detected for a speculative job, that job is flushed. To ensure prompt and proper service for the users of the service network, flushed jobs are quickly restarted directly from the job queue.

10. 发明公开

EP3350719A1 BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER 有权转让
公开(公告)号：EP3350719A1
公开(公告)日：2018-07-25
申请号：EP16775383.9
申请日：2016-09-13
申请人： Microsoft Technology Licensing, LLC
发明人： BURGER, Douglas C. , SMITH, Aaron L.
IPC分类号： G06F15/78 , G06F9/38
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

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