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1. 发明公开

EP0841667A2 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译： Flash-löschbareHalbleiterspeicheranordnung mit verbesserterZuverlässigkeit
公开(公告)号：EP0841667A2
公开(公告)日：1998-05-13
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写控制信号时，写信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

2. 发明公开

EP0841667A3 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：具有改善的可靠性的Flash可擦除半导体存储装置
公开(公告)号：EP0841667A3
公开(公告)日：1999-06-16
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

3. 发明授权

EP1126473B1 Semiconductor memory device 失效
标题翻译：半导体存储装置
公开(公告)号：EP1126473B1
公开(公告)日：2004-02-18
申请号：EP01109362.2
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

4. 发明公开

EP1126472A1 Flash-erasable semiconductor memory device 失效
标题翻译： LöschbareFlash-Halbleiterspeichervorrichtung
公开(公告)号：EP1126472A1
公开(公告)日：2001-08-22
申请号：EP01109361.4
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region, and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; addressing means supplied with address data for selecting a memory cell transistor in said memory cell array; writing means for writing information into said selected memory cell transistor; reading means for reading information from said selected memory cell transistor; and erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously, said erasing means erasing information by removing electric charges from said floating gate electrodes of said memory cell transistors by causing to flow a tunneling current through said gate insulation film; said memory cell array comprising a first memory cell array that includes a plurality of bit lines and a second memory cell array that includes also a plurality of bit lines, said source region of said plurality of memory cell transistors in said first and second memory cell arrays being connected, when erasing information, commonly to said erasing means for simultaneous erasing; said addressing means comprising a first addressing unit supplied with said address data for selecting a bit line in said first memory cell array and a second addressing unit supplied with said address data for selecting a bit line in said second memory cell array; address control means supplied with said address data for enabling one of said first and second addressing units while disabling the other of said first and second addressing units in response to said address data; and overriding means supplied with a control signal for selectively enabling one of said first and second addressing units in response to a first state of said control signal and for selectively enabling the other of said first and second addressing units in response to a second state of said control signal.
摘要翻译：一种闪存可擦除半导体存储器件，包括：包括多个存储单元晶体管的存储单元阵列，每个所述存储单元晶体管包括：设置在半导体衬底上的绝缘浮置栅极，用于存储电子形式的信息收费; 栅极绝缘膜，设置在所述半导体衬底的上主表面上，用于将所述浮置栅极与所述半导体衬底分离; 对应于所述浮栅电极限定在所述半导体衬底中的沟道区; 在所述浮置栅极的两侧限定在所述半导体衬底中的源极区域和漏极区域，所述源极区域将载流子注入到所述沟道区域中，使得所述载流子沿着所述沟道区域传输，而所述漏极区域收集载流子被注入所述沟道区域在所述源极区域被传送通过所述沟道区域，以及控制电极，所述控制电极通过所述电容器绝缘膜与所述浮动栅极分开设置，用于控制载流子从所述沟道区域经由所述栅极绝缘体从所述沟道区域注入所述浮置栅极电影; 提供有用于选择所述存储单元阵列中的存储单元晶体管的地址数据的寻址装置; 用于将信息写入所述选择的存储单元晶体管的写入装置; 用于从所述选择的存储单元晶体管读取信息的读取装置; 以及用于同时从包括在所述存储单元阵列中的多个存储单元晶体管擦除信息的擦除装置，所述擦除装置通过使隧道电流流过所述栅极而从所述存储单元晶体管的所述浮置栅电极去除电荷来擦除信息，绝缘膜; 所述存储单元阵列包括包括多个位线的第一存储单元阵列和还包括多个位线的第二存储单元阵列，所述第一和第二存储单元阵列中的所述多个存储单元晶体管的所述源极区当擦除信息时，通常连接到用于同时擦除的所述擦除装置; 所述寻址装置包括提供有用于选择所述第一存储单元阵列中的位线的所述地址数据的第一寻址单元和提供有用于选择所述第二存储单元阵列中的位线的所述地址数据的第二寻址单元; 提供有所述地址数据的地址控制装置，用于启用所述第一和第二寻址单元之一，同时响应于所述地址数据禁用所述第一和第二寻址单元中的另一个; 以及提供有控制信号的覆盖装置，用于响应于所述控制信号的第一状态选择性地使得所述第一和第二寻址单元之一响应于所述第一和第二寻址单元中的另一个响应所述第一和第二寻址单元的第二状态控制信号。

5. 发明授权

EP1126474B1 Semiconductor memory device 失效
公开(公告)号：EP1126474B1
公开(公告)日：2003-03-05
申请号：EP01109363.0
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

6. 发明授权

EP1126472B1 Flash-erasable semiconductor memory device 失效
标题翻译：闪存可擦除半导体存储装置
公开(公告)号：EP1126472B1
公开(公告)日：2003-03-05
申请号：EP01109361.4
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

7. 发明公开

EP1126474A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP1126474A1
公开(公告)日：2001-08-22
申请号：EP01109363.0
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A semiconductor memory device characterized by: a memory cell array including a plurality of memory cells arranged in rows and columns, said memory cell array comprising a first group array and a second group array each including a plurality of memory cell blocks, each of said memory cell blocks including a plurality of memory cells and at least one bit line to which said plurality of memory cells are connected, each of said memory cell blocks in said second group array having a corresponding memory cell block in said first group array, so that said memory cell block in said first group array and said memory cell block in said second group array and corresponding to each other form an adjoint pair; first addressing means supplied with address data for selecting a memory cell block in said first group array in response thereto, said first addressing means further selecting a bit line in said selected memory cell block; second addressing means supplied with said address data for selecting a memory cell block in said second group array in response thereto, said second addressing means further selecting a bit line in said selected memory cell block; selection control means supplied with said address data for controlling said first addressing means and said second addressing means for prohibiting the selection of a memory cell block in said first group array and a memory cell block in said second group array that form an adjoint pair; said memory cell blocks that form an adjoint pair having respective input/output lines for writing and/or reading information to and from a selected memory cell transistor that are connected commonly to a common input/output line, said common input/output line being provided in number corresponding to the number of said adjoint pairs; and switching means connected on the one hand with said plurality of input/output lines and on the other hand with input/output means for writing and/or reading information to and from a selected memory cell transistor, said switching means being controlled by said selection control means and connecting one of said input/output lines to said input/output means selectively in response to said address data.
摘要翻译： 1，一种半导体存储器件，其特征在于：包括按行和列排列的多个存储单元的存储单元阵列，所述存储单元阵列包括第一组阵列和第二组阵列，每个阵列包括多个存储单元块，每个所述存储器包括多个存储单元和与所述多个存储单元连接的至少一个位线的单元块，所述第二组阵列中的每个所述存储单元块在所述第一组阵列中具有对应的存储单元块，使得所述所述第一组阵列中的存储器单元块和所述第二组阵列中的所述存储器单元块并且彼此对应形成伴随对; 第一寻址装置被提供有地址数据，用于响应于此选择所述第一组阵列中的存储单元块，所述第一寻址装置还选择所述被选存储单元块中的位线; 第二寻址装置，其被提供有所述地址数据，用于响应于此选择所述第二组阵列中的存储单元块，所述第二寻址装置还选择所述选中的存储单元块中的位线; 选择控制装置，提供有用于控制所述第一寻址装置的所述地址数据和用于禁止选择形成伴随对的所述第一组阵列中的存储单元块和所述第二组阵列中的存储单元块的所述第二寻址装置; 所述存储器单元块形成伴随对，所述伴随对具有用于向共同连接到公共输入/输出线的选定存储器单元晶体管写入和/或读取信息的相应输入/输出线，所述公共输入/输出线被提供其数目对应于所述伴随对的数目; 以及一方面与所述多条输入/输出线连接并且另一方面与输入/输出装置连接的切换装置，所述输入/输出装置用于向所选择的存储器单元晶体管写入信息和/或从所选择的存储器单元晶体管读取信息，所述切换装置由所述选择控制装置并且响应于所述地址数据选择性地将所述输入/输出线之一连接到所述输入/输出装置。

8. 发明授权

EP0841667B1 Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：具有改善的可靠性的Flash可擦除半导体存储装置
公开(公告)号：EP0841667B1
公开(公告)日：2002-03-06
申请号：EP97119754.6
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige , Kajita, Tatsuya , Watanabe, Hisayoshi , Yamashita. Minoru
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543

9. 发明公开

EP1126473A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP1126473A1
公开(公告)日：2001-08-22
申请号：EP01109362.2
申请日：1992-11-20
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Akaogi, Takao , Ogawa, Yasushige
IPC分类号： G11C16/08 , G11C16/16 , G06F11/20
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A semiconductor memory device, comprising: a main memory cell array including therein a plurality of memory cells arranged in rows and columns, said main memory cell array including a plurality of bit lines each of which being connected with a plurality of memory cells; a redundant memory cell array (11 CR ) including therein a plurality of memory cells arranged in rows and columns, said redundant memory cell array including a plurality of bit lines each of which being connected with a plurality of memory cells, said plurality of bit lines in said redundant memory cell array being connected commonly to a common column line via respective column switches; a utility memory cell array (11 UT ) including therein a plurality of memory cells arranged in rows and columns, said utility memory cell array including a plurality of bit lines each of which being connected with a plurality of memory cells, said plurality of bit lines in said utility memory cell array being connected commonly to a common line; and input/output means connected to a data bus for writing and/or reading information to and from a selected memory cell via said data bus; wherein said semiconductor memory device comprises: addressing means (15) provided commonly to said redundant memory cell array and said utility memory cell array, said addressing means being supplied with address data for selecting a bit line in both of said redundant memory cell array and said utility memory cell array; and memory cell array selection means (SW 1 , SW 2 ) supplied with a control signal for selectively connecting said common column line of a selected memory cell array that is either said redundant memory cell array or said utility memory cell array, to input/output means via said data bus in response to said control signal; said addressing means (15) being supplied with said control signal for selecting one of the bit lines in either of said redundant memory cell array and said utility memory cell array in response to said control signal.
摘要翻译：一种半导体存储器件，包括：主存储单元阵列，其中包括按行和列排列的多个存储单元，所述主存储单元阵列包括多个位线，每个位线与多个存储单元连接; 冗余存储单元阵列（11CR），其中包括按行和列排列的多个存储单元，所述冗余存储单元阵列包括多个位线，每个位线与多个存储单元连接，所述多个位线在所述冗余存储单元阵列通过各自的列开关共同连接到公共列线; 其中包括以行和列排列的多个存储器单元的有用存储器单元阵列（11UT），所述有用存储器单元阵列包括多个位线，每个位线与多个存储器单元连接，所述多个位线在所述实用存储单元阵列共同连接到公共线; 和连接到数据总线的输入/输出装置，用于通过所述数据总线向所选存储单元写入和/或从所述存储单元读取信息; 其中所述半导体存储器件包括：寻址装置（15），共同地提供给所述冗余存储单元阵列和所述实用存储单元阵列，所述寻址装置被提供有用于选择所述冗余存储单元阵列和所述冗余存储单元阵列中的位线的地址数据实用存储单元阵列; 以及提供有控制信号的存储单元阵列选择装置（SW1，SW2），用于选择性地将作为所述冗余存储单元阵列或所述实用存储单元阵列的所选存储单元阵列的所述公共列线连接到输入/输出装置，所述数据总线响应于所述控制信号; 所述寻址装置（15）被提供有所述控制信号，用于响应于所述控制信号而在所述冗余存储单元阵列和所述有用存储单元阵列中的任一个中选择一条位线。

10. 发明公开

EP1168362A2 Flash memory with improved erasability and its circuitry 失效
标题翻译：闪光灯BessereLöschbarkeit和Schaltungen dazu
公开(公告)号：EP1168362A2
公开(公告)日：2002-01-02
申请号：EP01121238.8
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.
摘要翻译：闪存包括单元矩阵，其中可重写非易失性存储单元（591ij）布置在多个字线（WLi）和多个位线（BLi）之间的交叉处，并且还包括用于施加的行解码器（587）在写入或读取期间选择性地将字线（WLi）指定电压。闪存还包括：与字线相关联地位于单元矩阵和行解码器（587）之间的开关电路（590i），并且当字线被设置为负电压并进入在任何其他场合进行国家; 其负电压输出端子（554）连接到字线（WLi）的负电压偏置电路（592），并且响应于时钟脉冲（CLK）将负电源的电压输出施加到字线）; 以及时钟脉冲控制电路（593,594），用于当擦除字线（WLi）被选择时检测到时钟脉冲（CLK）被提供给负电压偏置电路。字线（WLi）被分成多个组，时钟脉冲控制电路（593,594）可操作以使时钟脉冲（CLK）被提供给连接到所选择的每个负电压偏置电路选择组中的任何字线时，组中的字线。

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