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1. 发明公开

EP0345162A1 Wafer scale integration device 失效
标题翻译： Integrierte Vorrichtung在Halbleiterscheibengrösse。
公开(公告)号：EP0345162A1
公开(公告)日：1989-12-06
申请号：EP89401508.0
申请日：1989-06-01
申请人： FUJITSU LIMITED
发明人： Tatematsu, Takeo
IPC分类号： H01L27/04 , H01L23/50 , H01L23/52 , G06F11/20
CPC分类号： H01L23/5286 , G11C5/063 , G11C29/006 , H01L23/52 , H01L24/45 , H01L24/49 , H01L2224/45124 , H01L2224/4911 , H01L2924/01039 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A wafer scale integration device comprises a plurality of real chips (2 R1 ,2 R2 ) formed in the center portion of a wafer (1) and a plurality of dummy chips (2 D ) formed in the circumference of the wafer (1). The dummy chips (2 D ) only include relay pads (7), some of the relay pads (7) are used for relaying bonding wires of power supply lines (4). Consequently, the power supply lines (4) do not short-circuit at edge portions of the wafer (1), since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad (7) connected to the bonding wire.
摘要翻译：晶片级整合器件包括形成在晶片（1）的中心部分的多个真实芯片（2R1,2R2）和形成在晶片（1）周边的多个虚设芯片（2D）。虚拟芯片（2D）仅包括继电器垫（7），一些继电器垫（7）用于中继电源线（4）的接合线。因此，电源线（4）在晶片（1）的边缘部分不会发生短路，因为由于连接到晶片（1）的继电器垫（7）而在晶片的边缘部分处的接合线的长度变短接合线。

2. 发明授权

EP0083210B1 A semiconductor device which prevents soft errors 失效
标题翻译：一种防止软错误的半导体器件
公开(公告)号：EP0083210B1
公开(公告)日：1986-11-26
申请号：EP82306891.1
申请日：1982-12-23
申请人： FUJITSU LIMITED
发明人： Tatematsu, Takeo
IPC分类号： H01L27/10 , H01L21/26
CPC分类号： H01L27/10805 , H01L23/556 , H01L2924/0002 , H01L2924/00

3. 发明授权

EP0373885B1 Semiconductor integrated device having pairs of undecided voltage portions 失效
标题翻译：与对不定电压的集成半导体器件
公开(公告)号：EP0373885B1
公开(公告)日：1996-02-28
申请号：EP89312971.8
申请日：1989-12-12
申请人： FUJITSU LIMITED
发明人： Nishiguchi, Tadao , Tatematsu, Takeo , Kasuta, Yoshinori
IPC分类号： G11C11/409 , G11C11/407 , G11C5/06 , G11C5/14
CPC分类号： G11C11/4097

4. 发明授权

EP0345162B1 Wafer scale integration device 失效
标题翻译：在晶片尺寸的集成器件。
公开(公告)号：EP0345162B1
公开(公告)日：1994-08-31
申请号：EP89401508.0
申请日：1989-06-01
申请人： FUJITSU LIMITED
发明人： Tatematsu, Takeo
IPC分类号： H01L27/04 , H01L23/50 , H01L23/52 , G06F11/20
CPC分类号： H01L23/5286 , G11C5/063 , G11C29/006 , H01L23/52 , H01L24/45 , H01L24/49 , H01L2224/45124 , H01L2224/4911 , H01L2924/01039 , H01L2924/14 , H01L2924/3011 , H01L2924/00014 , H01L2924/00

5. 发明授权

EP0419117B1 Wafer-scale semiconductor device having fail-safe circuit 失效
标题翻译：以更可靠的电路盘区域的半导体器件。
公开(公告)号：EP0419117B1
公开(公告)日：1995-04-12
申请号：EP90309969.5
申请日：1990-09-12
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki , Tatematsu, Takeo
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G11C29/78 , G11C29/006 , G11C29/832
摘要： A wafer-scale semiconductor memory device includes a wafer (1), and a plurality of memory chips (2) formed on the wafer. The memory chips contain a memory chip which includes a storage circuit (11, 21), and a switching transistor (QA) which selectively connects the storage circuit to a power supply line (Vcc) in response to a control signal (G, G1). The memory chip also includes a control logic circuit (12; 22, 24) which writes data into the storage circuit and reads out data from the storage circuit and which generates a logic signal used for controlling the transistor. Further, the memory chip includes a fail-safe circuit (13, 23, 23A) having a circuit element (F, G) having a status showing whether or not the control logic circuit is malfunctioning. The fail-safe circuit generates the control signal from the logic signal and the status of the circuit element so that when the circuit element has the status showing that the control logic circuit is malfunctioning, the fail-safe circuit outputs the control signal which instructs the switching element to disconnect the storage circuit from the power supply line irrespective of the logic signal.

6. 发明公开

EP0413590A3 Wafer scale integrated circuit device 失效
标题翻译： WAFER SCALE集成电路设备
公开(公告)号：EP0413590A3
公开(公告)日：1991-07-31
申请号：EP90309032.2
申请日：1990-08-17
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki , Tokoro, Masahiro , Nomura, Yukihiro , Tatematsu, Takeo
IPC分类号： G11C5/14 , G11C5/06 , G06F11/20 , G11C7/00 , G11C8/00
CPC分类号： G11C5/14 , G11C5/063
摘要： In a wafer scale integrated circuit device having functional blocks (2 11 ,2 12 ,...2 nm ) in rows and columns on the wafer (1) each of blocks are interconnected by local lines, power supply lines, and input signal lines constituted by a command signal transmitting line (43) and a wafer clock signal transmitting line (42). Input protection (5 11 ,5 12 ,...5 nm ; 6 11 ,6 12 ...6 nm ) for preventing an overshot or undershot level of the input signal are provided between each functional block and the command signal transmitting line (43) and the wafer clock signal transmitting line (42). Consequently, the input command signal (CMND) and the wafer clock signal (WCK) are delayed and rounded to the same degree for each and every functional block. Therefore, a high operational speed with a small operational margin can be realized by preventing synchronization error.

7. 发明公开

EP0419117A2 Wafer-scale semiconductor device having fail-safe circuit 失效
标题翻译： Scheibenbereichhalbleitergerätmit betriebssicherer Schaltung。
公开(公告)号：EP0419117A2
公开(公告)日：1991-03-27
申请号：EP90309969.5
申请日：1990-09-12
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki , Tatematsu, Takeo
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G11C29/78 , G11C29/006 , G11C29/832
摘要： A wafer-scale semiconductor memory device includes a wafer (1), and a plurality of memory chips (2) formed on the wafer. The memory chips contain a memory chip which includes a storage circuit (11, 21), and a switching transistor (QA) which selectively connects the storage circuit to a power supply line (Vcc) in response to a control signal (G, G1). The memory chip also includes a control logic circuit (12; 22, 24) which writes data into the storage circuit and reads out data from the storage circuit and which generates a logic signal used for controlling the transistor. Further, the memory chip includes a fail-safe circuit (13, 23, 23A) having a circuit element (F, G) having a status showing whether or not the control logic circuit is malfunctioning. The fail-safe circuit generates the control signal from the logic signal and the status of the circuit element so that when the circuit element has the status showing that the control logic circuit is malfunctioning, the fail-safe circuit outputs the control signal which instructs the switching element to disconnect the storage circuit from the power supply line irrespective of the logic signal.
摘要翻译：晶片级半导体存储器件包括晶片（1）和形成在晶片上的多个存储器芯片（2）。存储器芯片包括存储芯片，其包括存储电路（11,21）和响应于控制信号（G，G1）选择性地将存储电路连接到电源线（Vcc）的开关晶体管（QA）。存储器芯片还包括一个控制逻辑电路（12; 22,24），它将数据写入存储电路并从存储电路中读出数据，并产生用于控制晶体管的逻辑信号。此外，存储器芯片包括具有电路元件（F，G）的故障保护电路（13,23,23A），该电路元件具有表示控制逻辑电路是否发生故障的状态。故障保护电路从逻辑信号和电路元件的状态产生控制信号，使得当电路元件具有表示控制逻辑电路发生故障的状态时，故障保护电路输出指示开关元件以断开存储电路与电源线的连接，而与逻辑信号无关。

8. 发明公开

EP0213037A2 Semiconductor memory device having test pattern generating circuit 失效
标题翻译：与Prüfmustergeberschaltung半导体存储装置。
公开(公告)号：EP0213037A2
公开(公告)日：1987-03-04
申请号：EP86401767.8
申请日：1986-08-07
申请人： FUJITSU LIMITED
发明人： Tatematsu, Takeo
IPC分类号： G11C29/00
CPC分类号： G11C29/36
摘要： A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit (10); an element for receiving external signals supplied from the outside; and an input switching circuit (20) connected between the test pattern generating circuit (10) and the receiving element, for switching the input supplied to the internal circuit between output signals generated from the test pattern generating circuit (10) and the external signals, the output signals generated from the test pattern generating circuit (10) being input to the internal circuit through the input switching circuit (20) in a test mode, the external signals being input to the internal circuit through the input switching circuit (20) in a usal mode; the test pattern generating circuit (10), the input switching circuit (20), and the internal circuit being provided on the same chip.

9. 发明公开

EP0055129A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0055129A3
公开(公告)日：1984-07-04
申请号：EP81306047
申请日：1981-12-22
申请人： FUJITSU LIMITED
发明人： Tatematsu, Takeo
IPC分类号： G11C29/00
CPC分类号： G11C29/34
摘要： A semiconductor memory device includes a plurality of memory blocks (1-1,1-2,1-3,1-4) each comprising memory cells arranged in rows and columns, a plurality of pairs of data buses (DB 1 , DB 1 ; ... DB 4 , DB 4 ) connected respectively to the said memory blocks, cell selection means (2,3, 4, 5) for selecting one memory cell in each memory block so as to place the selected memory cells in simultaneous connection with the respective data buses, and write circuitry (6, 7) for writing preselected input data into each of the selected memory cells. The device is provided with a read test circuit (10) operable, on the basis of a set of signals received respectively by way of all the said pairs of data buses simultaneously, to provide a fault-indicating response if the said set of signals differs from a predetermined desired set appropriate to desired normal operation of the device. Such testing of one memory cell from each memory block simultaneously can serve to reduce the time needed to test the memory device as a whole.
摘要翻译：一种半导体存储器件包括多个存储块（1-1,1-2,1-3,1-4），每个存储块包括按行和列排列的存储单元，多对数据总线（DB1，DB1; ...）。 ...，DB4，DB4）;单元选择装置（2,3,4,5），用于选择每个存储块中的一个存储单元，以便将选择的存储单元与相应的数据同时连接总线和写入电路（6,7），用于将预选输入数据写入到每个选定存储单元中。该装置具有读取测试电路（10），该读取测试电路基于分别通过所有所述数据总线对同时接收的一组信号来操作，以在所述一组信号不同时提供故障指示响应从适合于设备的期望的正常操作的预定期望的设置。同时对来自每个存储器块的一个存储器单元的这种测试可以用于减少作为整体测试存储器器件所需的时间。

10. 发明公开

EP0418777A2 Wafer scale semiconductor device 失效
标题翻译： Halbleiteranordnung au Scheibenskala。
公开(公告)号：EP0418777A2
公开(公告)日：1991-03-27
申请号：EP90117852.5
申请日：1990-09-17
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki , Tokoro, Masahiro , Nomura, Yukihiro , Tatematsu, Takeo
IPC分类号： H01L27/04 , H01L23/485
CPC分类号： H01L24/05 , H01L23/52 , H01L23/5329 , H01L23/53295 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/48091 , H01L2224/4813 , H01L2224/48451 , H01L2224/48463 , H01L2224/4911 , H01L2224/49175 , H01L2224/85424 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A wafer scale semiconductor device provides a bonding pad, the bonding pad comprising: an electrically floating conductor layer (13) contactable with a bonding wire, an insulating layer (22) formed under the conductor layer, and a buffer layer (21) formed under the insulating layer in a manner that the shape of the buffer layer corresponds to that of the conductor layer the buffer layer adsorbing an applied shock.
摘要翻译：晶圆级半导体器件提供接合焊盘，所述焊盘包括：与接合线接触的电浮动导体层（13），形成在所述导体层下面的绝缘层（22）和形成在所述导体层下面的缓冲层（21）所述绝缘层的缓冲层的形状对应于缓冲层吸附施加冲击的导体层的形状。

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