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1. 发明公开

EP3392908A1 LEISTUNGSHALBLEITERANORDNUNG MIT EINEM STAPEL VON EINE VERBESSERTE GEOMETRIE AUFWEISENDEN ANSCHLUSSPLATTEN ZUR GEMEINSAMEN ELEKTRISCHEN KONTAKTIERUNGEN MEHRERER, GLEICHARTIGER LEISTUNGSHALBLEITER-SCHALTELEMENTE 有权
公开(公告)号：EP3392908A1
公开(公告)日：2018-10-24
申请号：EP17167264.5
申请日：2017-04-20
申请人： Infineon Technologies AG
发明人： WISSEN, Matthias , GROOVE, Andreas , DOMES, Daniel
IPC分类号： H01L25/11 , H05K1/02
CPC分类号： H01L25/105 , H01L23/3675 , H01L23/4922 , H01L23/50 , H01L23/52 , H01L25/115 , H01L25/117
摘要： Leistungshalbleiteranordnung (1) mit einer Mehrzahl von in einer Reihe angeordneten Leistungshalbleiter-Schaltelemente (2a, 2b, 2c, 2d), wobei jedes Leistungshalbleiter-Schaltelement (2a, 2b, 2c, 2d) einen Laststromanschluss (3a) für eine Laststromzufuhr (S) und einen Laststromanschluss (3b) für eine Laststromabfuhr aufweist, und die Laststromanschlüsse (3a, 3b) auf einer gemeinsamen Linie (L) angeordnet sind, wobei die Leistungshalbleiteranordnung (1) ferner jeweils eine Anschlussplatte (4a; 4b) pro Laststromrichtung aufweist, wobei die Anschlussplatten (4a, 4b) elektrisch isoliert zueinander in einer Stapelrichtung (R) gestapelt sind, wobei
wenigstens eine der Anschlussplatten (4a; 4b) mehrfach mittels Schlitzen (S) geschlitzt ist, so dass die Anschlussplatte (4a, 4b) jeweils durch die Schlitze (S) definierte Sektionen (SC1, SC2, SC3, SC4) ausbildet, und benachbarte Sektionen (SC1, SC2, SC3, SC4) lediglich an der Einspeisungskante (EK) elektrisch leitend verbunden sind; und/oder wenigstens eine der Anschlussplatten (4a, 4b) entlang der Längskanten (LK) unter der Ausbildung eines Winkelabschnitts (5b) abgekantet ist.

2. 发明公开

EP3238219A1 LOW CROSSTALK MAGNETIC DEVICES 审中-公开
标题翻译：低串扰磁性器件
公开(公告)号：EP3238219A1
公开(公告)日：2017-11-01
申请号：EP15872024.3
申请日：2015-12-15
申请人： Nokia Technologies OY
发明人： VILANDER, Ari
IPC分类号： H01F17/00 , H01F27/38 , H01F27/36 , G01R33/02
CPC分类号： H01F27/34 , G01R33/0023 , H01F27/346 , H01F27/42 , H01L23/52 , H01L23/5225
摘要： In one aspect there is an apparatus. The apparatus may include an electronic circuit that generates a first magnetic field from a current in the electronic circuit. The apparatus may further include a sensing circuit separated from the electronic circuit by a predetermined distance to sense the first magnetic field. A cage circuit may cancel a portion of the first magnetic field at the sensing circuit. The cage circuit may generate a cage current from the current in the electronic circuit and at least one of a phase shift or an amplitude shift applied to the current in the electronic circuit. The cage current may generate a second magnetic field causing cancellation of the portion of the magnetic field from the electronic circuit at the sensing circuit.
摘要翻译：一方面有一种装置。该设备可以包括电子电路（150），其根据电子电路中的电流生成第一磁场。该装置可以进一步包括与电子电路分开预定距离（350）以感测第一磁场的感测电路（320）。笼型电路（140）可以在感测电路（320）处消除第一磁场的一部分。笼形电路（140）可以根据电子电路（150）中的电流以及施加到电子电路中的电流的相移或幅度偏移中的至少一个来生成笼电流。笼电流可以产生第二磁场，导致在感测电路（320）处从电子电路消除部分磁场。

3. 发明公开

EP1433202A2 INTEGRATION OF BARRIER LAYER AND SEED LAYER 审中-公开
标题翻译：积分对阻挡层和籽晶层
公开(公告)号：EP1433202A2
公开(公告)日：2004-06-30
申请号：EP02757668.5
申请日：2002-09-09
申请人： Applied Materials Inc.
发明人： CHUNG, Hua , CHEN, Ling , YU, Jick , CHANG, Mei
IPC分类号： H01L21/768
CPC分类号： C23C14/06 , C23C30/00 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L2924/0002 , H01L2924/00
摘要： The present invention generally relates to filling of a feature by depositing a barrier layer (1204), depositing a seed layer (1502) over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed layer deposited over the barrier layer. For example, the copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. In another embodiment, the seed layer comprises a copper alloy seed layer (1512) deposited over the barrier layer and a second seed layer (1514) deposited over the copper alloy seed layer. The copper alloy seed layer may comprise copper and a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof The second seed layer may comprise a metal, such as undoped copper. In still another embodiment, the seed layer comprises a first seed layer and a second seed layer. The first seed layer may comprise a metal, such as aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second seed layer may comprise a metal, such as undoped copper.

4. 发明公开

EP1069206A2 Nanoscale conductive connectors and method for making same 审中-公开
标题翻译：纳米导电连接器及其制造方法
公开(公告)号：EP1069206A2
公开(公告)日：2001-01-17
申请号：EP00305578.7
申请日：2000-07-03
申请人： LUCENT TECHNOLOGIES INC.
发明人： Moon Choi, Kyung , Jin, Sungho
IPC分类号： C23C16/26 , C23C16/00 , H01L23/49
CPC分类号： H01L24/10 , B82Y10/00 , B82Y30/00 , C30B25/00 , C30B29/605 , H01L21/288 , H01L21/76838 , H01L23/52 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/13 , H01L2224/13099 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , Y10S977/72 , Y10S977/742 , Y10S977/745 , Y10S977/762 , Y10S977/843 , Y10S977/932 , H01L2224/48 , H01L2924/00
摘要： Nanoscale connectors particularly useful for connecting microscale devices comprise free-standing nanoscale conductors. The nanoscale conductors are conveniently fabricated in sets of controlled, preferably equal length by providing a removable substrate, growing conductive nanotubes or nanowires on the substrate, equalizing the length of the nanoscale conductors, and removing the substrate. Preferably the removable substrate is soluble, leaving a collection of free standing nanoscale connectors in suspension or solution.
摘要翻译：特别适用于连接微型器件的纳米级连接器包括自立式纳米级导体。通过提供可移除衬底，在衬底上生长导电纳米管或纳米线，均衡纳米导体的长度以及去除衬底，纳米级导体便利地以一组受控的，优选等长的方式制造。优选地，可去除的基材是可溶的，留下独立的纳米级连接器在悬浮液或溶液中的集合。

5. 发明授权

EP0418802B1 Wiring structure in a wafer-scale integrated circuit 失效
标题翻译：导体结构与晶片上grösstintegrierter电路
公开(公告)号：EP0418802B1
公开(公告)日：1997-02-12
申请号：EP90117908.5
申请日：1990-09-18
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Murao, Toshiaki, c/o Fujitsu Limited , Kikuchi, Takeo, c/o Fujitsu Limited , Iryu, Toshihiko, c/o Fujitsu Limited , Sugamoto, Hiroyuki, c/o Fujitsu Limited , Nomura, Hidenori, c/o Fujitsu Limited
IPC分类号： H01L23/52 , H01L23/528 , G06F11/20
CPC分类号： H01L23/5286 , H01L23/52 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/85205 , H01L2924/00014 , H01L2924/14 , H01L2924/30107 , H01L2924/20753 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/00 , H01L2924/2075 , H01L2924/2076 , H01L2924/20754 , H01L2224/05599
摘要： A semiconductor wafer-scale integrated circuit comprising:- a single wafer (11; 11 min ); a plurality of functional blocks (12A, 12B, etc.) formed on said wafer; layered wiring (13; 13A, 13B, etc.) interconnecting predetermined connection electrodes (14) provided respectively in each of said functional blocks; and bonding wire (17; 17A, 17B, etc.) interconnecting said connection electrodes (14) provided respectively in each of said functional blocks, in addition to and electrically in parallel with said layered wiring.

6. 发明授权

EP0326828B1 Leistungstransistor 失效
标题翻译：功率晶体管
公开(公告)号：EP0326828B1
公开(公告)日：1996-09-04
申请号：EP89100574.6
申请日：1989-01-13
申请人： ROBERT BOSCH GMBH
发明人： Conzelmann, Gerhard, Dipl.-Phys. , Fiedler, Gerhard, Dipl.-Ing. (FH) , Olbrich, Ludger, Dipl.-Phys.
IPC分类号： H01L29/732 , H01L23/52 , H01L27/06
CPC分类号： H01L29/73 , H01L23/52 , H01L27/0211 , H01L2224/48091 , H01L2224/49109 , H01L2224/49113 , H01L2224/49433 , H01L2924/10253 , H01L2924/00 , H01L2924/00014

7. 发明公开

EP0593637A4 LOW IMPEDANCE BUS FOR POWER ELECTRONICS. 失效
标题翻译： SAMMELSCHIENE FUR LEISTUNGSELEKTRONIK MIT NIEDRIGEN IMPEDANZ。
公开(公告)号：EP0593637A4
公开(公告)日：1994-11-23
申请号：EP92915428
申请日：1992-07-09
申请人： US WINDPOWER
发明人： DEAM DAVID R , ERDMAN WILLIAM L
IPC分类号： H01L23/52 , H01L25/11 , H02G5/00 , H02M7/00 , H02M1/10
CPC分类号： H01L25/115 , H01L23/52 , H01L2924/0002 , H01L2924/3011 , H02G5/005 , H02M7/003 , H01L2924/00
摘要： A low impedance, high power bus for conduction of electrical power with reduced transient signal effects is described herein. The high power bus can be applied as a high power supply bus between a constant voltage source and a plurality of switching cells positioning at varying locations along the bus, and as branch bus for the switching cells. The power bus can transmit high power: large currents in the hundreds or thousands of amperes, and large voltage potentials in the hundreds or thousands of volts. Particularly, the power bus has use in a DC-to-AC inverter that converts DC from a constant voltage source into three-phase AC for delivery to an electrical power grid. The high power bus includes two conductive bars positioned so that the current flow therethrough is balanced (equal and opposing), and the magnetic field is substantially confined between the bars. The bus includes a dielectric positioned between the conductive bars. In a preferred embodiment, the AC is conducted on extension bars that extend along the power supply bus, so that a main bus is created by the combination of the AC extension bars and the DC power supply bus, and the sum of the currents in the bars is approximately zero at all locations in the bus. The power bus lessens or even obviates the need for the snubber networks commonly used to reduce transients, and reduces the strength of magnetic fields and electric fields that could otherwise interfere with neighboring electrical components.
摘要翻译：本文描述了用于传导电功率的低阻抗高功率总线，具有减小的瞬态信号效应。高功率总线可以用作恒定电压源和沿着总线位于不同位置的多个开关单元之间的高电源总线，以及用作开关单元的分支总线。电源总线可以传输高功率：数百或数千安培的大电流，以及数百或数千伏特的大电压电位。特别地，电力总线用于将DC从恒定电压源转换成三相AC以传送到电力电力网的DC-AC逆变器。高功率总线包括两个导电棒，其定位成使得其中的电流通过其平衡（相等和相反），并且磁场基本上限制在杆之间。总线包括位于导电棒之间的电介质。在优选实施例中，AC在沿着电源总线延伸的延长杆上进行，使得通过AC延伸杆和DC电源总线的组合产生主总线，并且在巴士所有地点的酒吧大概为零。电源总线减轻甚至消除了通常用于减少瞬变的缓冲网络的需要，并且减小了否则会干扰相邻电气部件的磁场和电场的强度。

8. 发明公开

EP0527033A3 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：EP0527033A3
公开(公告)日：1993-12-15
申请号：EP92307117.9
申请日：1992-08-04
申请人： FUJI ELECTRIC CO. LTD.
发明人： Kobayashi, Shinichi, c/o Fuji Electric Co., Ltd. , Miyasaka, Tadashi, c/o Fuji Electric Co., Ltd. , Shimizu, Toshihisa, c/o Fuji Electric Co., Ltd.
IPC分类号： H01L23/64 , H01L25/07 , H01L23/52 , H01L23/498 , H01L23/495
CPC分类号： H01L23/52 , H01L23/49562 , H01L23/49811 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2924/00014 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： To prevent a semiconductor device from breaking down due to a surge voltage which is generated by the existence of floating inductance in a terminal conductor drawn out from the connection of two semiconductor elements contained in one semiconductor container and which is applied to one of the elements when they are turned off, the invention provides a semiconductor device in which two pairs of a first and a second pair of electrode conductors each consists of a pair of a first electrode conductor onto which semiconductor elements with main electrodes are fixed on its bottom surface and a second electrode conductor connected to the main electrodes on the upper surface on the semiconductor elements by connecting leads are fixed on the bottom plate of a container via insulating plates, one main terminal conductor connected to the first electrode conductor of the first pair and another main terminal conductor connected to the second electrode conductor of the second pair are both drawn out externally, and one intermediate terminal conductor is connected to both the second electrode conductor of the first pair and the first electrode conductor of the second pair and drawn out externally wherein connecting conductor with a lower floating inductance and a higher resistance than in the part of the intermediate terminal conductor between the second electrode conductor of the first pair and the first electrode conductor of the second pair is connected across both electrode conductors in parallel to the intermediate terminal conductor. When semiconductor elements are connected to the respective semiconductor elements in parallel, the connecting conductors are installed at locations close to each semiconductor element of the electrode conductors.
摘要翻译：为了防止半导体器件由于在从包含在一个半导体容器中的两个半导体元件的连接引出的端子导体中存在浮动电感而产生的浪涌电压击穿，它们被关断，本发明提供了一种半导体器件，其中两对第一和第二对电极导体分别由一对第一电极导体构成，其上具有主电极的半导体元件固定在其底表面上，通过连接引线连接到半导体元件上表面上的主电极的第二电极导体通过绝缘板固定在容器的底板上，一个主端子导体连接到第一对的第一电极导体，另一个主端子连接到第二对的第二电极导体的导体都被拉出 t，并且一个中间端子导体连接到第一对的第二电极导体和第二对的第一电极导体两者并且从外部引出，其中连接导体具有较低的浮动电感和高于在第一对的第二电极导体和第二对的第一电极导体之间的中间终端导体跨过与中间终端导体平行的两个电极导体连接。当半导体元件并联连接到各个半导体元件时，连接导体安装在靠近电极导体的每个半导体元件的位置处。

9. 发明公开

EP0468734A1 Semi-conductor device having circuits on both sides of insulation layer and ultrasonic signal path between the circuits 失效
标题翻译：具有在这些电路之间的绝缘层和超声波通信路径的两侧的电路的半导体器件。
公开(公告)号：EP0468734A1
公开(公告)日：1992-01-29
申请号：EP91306673.4
申请日：1991-07-23
申请人： FUJITSU LIMITED
发明人： Sasaki, Nobuo
IPC分类号： H01L21/768 , H01L27/20 , H01L41/08 , H03H9/50
CPC分类号： H01L27/20 , H01L23/52 , H01L23/535 , H01L24/73 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/73257 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having a semiconductor substrate (11) or an insulation layer (58), an integrated circuit on each side of the semiconductor substrate (11) or an insulation layer (58), and a path for an ultrasound signal connecting both integrated circuits. The path is realized through the semiconductor substrate (11) or insulation layer (58) by providing an ultrasonic transducer on each side of the semiconductor substrate (11) or an insulation layer (58). A plurality of paths may be provided in the same semiconductor substrate (11) or an insulation layer (58) without crosstalk by transmitting ultrasound signals having different frequencies through the respective paths. The paths may be one-way or two-way. The ultrasonic transducers (17a to 17d) each contain a piezoelectric material, and the thickness of the piezoelectric material (14a to 14d) in the ultrasonic transducer at least on a receiver side in each path is such that the resonant frequency of the ultrasonic transducer corresponds to the frequency of the ultrasound signal transmitted through the path. A plurality of paths transmitting an ultrasound signal having the same frequency may be provided between at least one point on one side and more than one point on the other side, through the semiconductor substrate (11) or insulation layer (58), when each of the paths is used in a time-sharing manner.
摘要翻译：具有在半导体基板（11）的每一侧或绝缘层（58）上的半导体基片（11）或上绝缘层（58），集成电路的半导体器件，并在超声信号连接两者的集成电路的路径，路径是通过提供至超声换能器在半导体基片的每一侧（11）或绝缘层（58）通过所述半导体衬底（11）或绝缘层（58）来实现。可以在相同的半导体衬底（11）或绝缘层（58）上通过发送具有通过respectivement路径不同的频率的超声信号被提供的路径的多个无串扰。该路径可以是单向或双向的。超声波换能器（17A到17D）各自包含在所述超声换能器至少在每个路径中的接收器侧的压电材料，压电材料的厚度（14a至14d）进行检测所做的超声换能器相对应的谐振频率到的超声信号的频率反式通过路径mitted。可以在至少一个点之间设置在一侧，而在另一侧的多个点的路径发射（具有相同的频率的超声波信号中的多个，通过所述半导体基片 11）或当每个路径的以时间共享方式使用绝缘层（58）。

10. 发明公开

EP0418777A2 Wafer scale semiconductor device 失效
标题翻译： Halbleiteranordnung au Scheibenskala。
公开(公告)号：EP0418777A2
公开(公告)日：1991-03-27
申请号：EP90117852.5
申请日：1990-09-17
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki , Tokoro, Masahiro , Nomura, Yukihiro , Tatematsu, Takeo
IPC分类号： H01L27/04 , H01L23/485
CPC分类号： H01L24/05 , H01L23/52 , H01L23/5329 , H01L23/53295 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/48091 , H01L2224/4813 , H01L2224/48451 , H01L2224/48463 , H01L2224/4911 , H01L2224/49175 , H01L2224/85424 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A wafer scale semiconductor device provides a bonding pad, the bonding pad comprising: an electrically floating conductor layer (13) contactable with a bonding wire, an insulating layer (22) formed under the conductor layer, and a buffer layer (21) formed under the insulating layer in a manner that the shape of the buffer layer corresponds to that of the conductor layer the buffer layer adsorbing an applied shock.
摘要翻译：晶圆级半导体器件提供接合焊盘，所述焊盘包括：与接合线接触的电浮动导体层（13），形成在所述导体层下面的绝缘层（22）和形成在所述导体层下面的缓冲层（21）所述绝缘层的缓冲层的形状对应于缓冲层吸附施加冲击的导体层的形状。

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