专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1891516A2 SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS 审中-公开
标题翻译：用于管道式微处理器中的节能的系统和方法
公开(公告)号：EP1891516A2
公开(公告)日：2008-02-27
申请号：EP06760325.8
申请日：2006-05-24
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/3824 , G06F9/3826
摘要： A system and method for preserving power in a microprocessor pipeline (300). The system includes a register file read control unit (305), the read control unit (305) being configured to monitor one or more outputs from a control /decode unit (205) of the pipeline (300) and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units (301, 303) each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units (301, 303) being coupled to a unique register port of a register file (109) within the pipeline (300). The input of each of the one or more read inhibit units (301, 303) being coupled to the control/decode unit (205), and the enable terminal of each of the one or more read inhibit units (301, 303) being coupled to a unique output of the read control unit (305).
摘要翻译：一种用于在微处理器管线（300）中保存功率的系统和方法。该系统包括寄存器文件读取控制单元（305），读取控制单元（305）被配置为监测来自流水线（300）的控制/解码单元（205）的一个或多个输出并且监视来自一个或多个管道的更多其他阶段。该系统还包括一个或多个读取禁止单元（301,303），每个读取禁止单元具有输入，输出和使能端子，一个或多个读取禁止单元（301,303）中的每一个的输出耦合到唯一的寄存器管道（300）内的寄存器文件（109）的端口。一个或多个读取禁止单元（301,303）中的每一个的输入端耦合到控制/解码单元（205），并且一个或多个读取禁止单元（301,303）中的每一个的使能端被耦合到读取控制单元（305）的唯一输出。

2. 发明授权

EP1891519B1 EFFICIENT SUBPROGRAM RETURN IN MICROPROCESSORS 有权
标题翻译：高效的子程序返回微处理器
公开(公告)号：EP1891519B1
公开(公告)日：2016-12-07
申请号：EP06771282.8
申请日：2006-05-25
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind , LUND, Morten, W.
IPC分类号： G06F9/38 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806

3. 发明公开

EP1891519A2 EFFICIENT SUBPROGRAM RETURN IN MICROPROCESSORS 有权
标题翻译：高效的子程序返回微处理器
公开(公告)号：EP1891519A2
公开(公告)日：2008-02-27
申请号：EP06771282.8
申请日：2006-05-25
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind , LUND, Morten, W.
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： A method and medium for performing subroutine return operations. Test operations (88, 90) are performed in parallel with other operations (92, 94) in a return operation (98) . These test operations (88, 90) and the return operations (96, 98) are performed in response to a single instruction (86) .

4. 发明公开

EP1875338A2 MICROPROCESSOR ACCESS OF OPERAND STACK AS A REGISTER FILE USING NATIVE INSTRUCTIONS 审中-公开
标题翻译：微处理器访问一个操作数堆栈，寄存器文件中使用原生指令
公开(公告)号：EP1875338A2
公开(公告)日：2008-01-09
申请号：EP06738096.4
申请日：2006-03-08
申请人： ATMEL CORPORATION
发明人： STROM, Oyvind , RENNO, Erik , MONSEN, Kristian
IPC分类号： G06F9/22
CPC分类号： G06F9/30134 , G06F9/3016 , G06F9/30196 , G06F9/321 , G06F9/3861
摘要： A combined native (RISC or CISC) microprocessor and stack (Java) machine (10, 11, 13) are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly (54) , while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode (56) . In order for native microcode instructions to access the Java operand stack, a Java operand stack pointer (22; 102) points to the register file (15; 90) location that is the current top of the stack (ToS) , while a remap bit (RM) in the status register (101) indicates that registers specified in native instructions are remapped (90a) as the maximum Java operand stack pointer value minus the present value of the Java operand stack pointer.

5. 发明公开

EP1410174A2 MICROPROCESSOR FOR EXECUTING BYTE COMPILED JAVA CODE 审中-公开
标题翻译：微处理器用于进行BYTEKOMPILIERTEN JAVA码
公开(公告)号：EP1410174A2
公开(公告)日：2004-04-21
申请号：EP02764161.2
申请日：2002-04-01
申请人： ATMEL CORPORATION
发明人： STROM, Oyvind
IPC分类号： G06F9/00
CPC分类号： G06F9/3017 , G06F9/30101 , G06F9/30134 , G06F9/30174 , G06F9/3879
摘要： A microprocessor architecture (30) for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module (31) sees the elements in the register file (35) as a circular operand stack and the RISC module (33) sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

6. 发明公开

EP1987424A2 PACKED ADD-SUBTRACT OPERATION IN A MICRPROCESSOR 审中-公开
标题翻译：密封在微处理器加减操作
公开(公告)号：EP1987424A2
公开(公告)日：2008-11-05
申请号：EP07710165.7
申请日：2007-01-17
申请人： ATMEL CORPORATION
发明人： PEDERSEN, Ronny , RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/44
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half word operands obtained from designated top (_T) or bottom (_B) half-word locations of; designated source registers (REGA, REGB) of a register file (19) and the sum and difference results of such operation are packed into respective top and bottom half - word locations of a designated destination register (DST_REG). The microprocessor includes an arithmetic-logic unit (ALU 11) with adder circuitry that can be selectively split into separate half -word adders (13, 15) that are independently selectable (ADDSUB_CTL_T, ADDSUB_CTL_B) to perform -either an addition operation or subtraction operation upon the selected half-word operands (OP_B_T, OP_A_T, OP_B_B, OP_AB). The half word adders of the ALU access the operands from source registers via a set of multiplexers (21 - 26) that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

7. 发明公开

EP1896937A2 APPARATUS AND METHOD FOR PERFORMING EFFICIENT MULTIPLY-ACCUMULATE OPERATIONS IN MICROPROCESSORS 审中-公开
标题翻译： DEVICE AND METHOD FOR PERFORMING高效运营乘以积累微处理器
公开(公告)号：EP1896937A2
公开(公告)日：2008-03-12
申请号：EP06744814.2
申请日：2006-05-26
申请人： Atmel Corporation
发明人： STROM, Oyvind , RENNO, Erik, Knutsen
IPC分类号： G06F9/302 , G06F7/544
CPC分类号： G06F9/3836 , G06F7/5443 , G06F9/3001 , G06F9/30101 , G06F9/30138 , G06F9/3824 , G06F9/3838 , G06F9/3857 , G06F9/3859
摘要： An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for storing an accumulator value internal to the apparatus, and control circuitry for controlling the operation of the apparatus.

8. 发明公开

EP1891532A1 EXTRACTED-INDEX ADDRESSING OF BYTE-ADDRESSABLE MEMORIES 审中-公开
标题翻译：寻址字节寻址存储索引提取
公开(公告)号：EP1891532A1
公开(公告)日：2008-02-27
申请号：EP06751727.6
申请日：2006-04-27
申请人： ATMEL CORPORATION
发明人： PEDERSEN, Ronny , RENNO, Erik, N. , STROM, Oyvind
IPC分类号： G06F12/06
CPC分类号： G06F9/355 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A microprocessor circuit useful for indexed addressing of byte -addressable memories includes word- length index, base address, and destination registers (Ri, Rb, Rd) designated by an instruction. The instruction also specifies one byte (t, u, l, b) packed within the index register (Ri), which is to be extracted. A multiplexer (15) has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control ( ) passes the specified byte to its output (17). The extracted byte is provided directly at specific bit positions of a zero-extended address offset word (19). The offset word is added (25) to the base address, the sum (ADDR) being used to address memory contents (27) that are loaded into the destination register (Rd).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式