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1. 发明公开

EP1388172A1 EEPROM CELL WITH ASYMMETRIC THIN WINDOW 审中-公开
标题翻译：不对称薄窗EEPROM单元
公开(公告)号：EP1388172A1
公开(公告)日：2004-02-11
申请号：EP02715090.3
申请日：2002-03-11
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L21/336 , H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/7883
摘要： A nonvolatile memory cell (80) is constructed with a charge transfer window (101) having a charge transfer region (101A) smaller than the minimum resolution feature size of used to construct the cell. The window (101) is constructed to the minimum feature size, but its layout position places it partly within the channel region of the cell and partly within a field oxide barrier wall (85b). The part of the window (101A) that lies within the channel region does not reach across the width of the channel to an apposing field oxide barrier wall (85a) and does not reach along the length of the channel region to either of opposedly laid source (91) and drain (93) regions. The oxide within the window (101) is evenly etched back to reveal the substrate (111) within the channel region. A thin tunneling oxide is then grown within the window (101), including the part of the window (101B) encompassing the field oxide barrier wall (85b).

2. 发明公开

EP1820213A2 MULTI-BIT NANOCRYSTAL MEMORY 审中-公开
标题翻译：多位-NANOKRISTALLSPEICHER
公开(公告)号：EP1820213A2
公开(公告)日：2007-08-22
申请号：EP05817129.9
申请日：2005-11-07
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L21/28114 , H01L21/28123 , H01L27/11521 , H01L29/42332 , H01L29/42376
摘要： An improved memory cell having a nanocrystal gate structure (Fig. 20) is formed by using a plurality of trenches (52, 57) in the manufacturing process. The nanocrystal gate structure (20) is comprised of a tunnel oxide layer (21), a nanocrystal layer (22), and a control oxide layer (23) over a substrate (10). A first trench (52) is formed and doped areas (54, 55) are formed in the substrate near the bottom of the first trench. After at least one doped area is formed, a portion of the nanocrystal structure (20) is removed. The first trench (31) is filled and a second trench (57) is formed that is positioned in close proximity to the location of the first trench. A second portion of the nanocrystal gate structure (20) is then removed near the bottom of the second trench. Using a plurality of trenches, the process reduces the size of the nanocrystal gate structure, thus improving the performance of the memory cell.

3. 发明公开

EP1665274A2 FOWLER-NORDHEIM BLOCK ALTERABLE EEPROM MEMORY CELL 审中-公开
标题翻译：下福勒诺德海姆BLOCK CHANGING EEPROM单元
公开(公告)号：EP1665274A2
公开(公告)日：2006-06-07
申请号：EP04778854.2
申请日：2004-07-21
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： G11C7/00
CPC分类号： H01L29/7883 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A block alterable memory cell (400) has a select control gate (408; 524) extending from a floating gate region (410; 520) to a drain region (402; 528). The block alterable memory cell comprises a substrate (401; 502) that further includes a source implant region (406), a buried implant region (404; 512), and active region (414; 514, 516) and a drain implant region (402; 528). A tunnel oxide layer (460; 518) overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. The select control gate comprises a first gate oxide layer (450; 517) overlying the substrate, an inter poly layer (412; 521) overlying over the floating gate (410; 520), and a second polysilicon layer (408; 524) extending over both the floating gate transistor region and the active region to an edge of the drain implant region.

4. 发明公开

EP1665356A2 METHOD OF MAKING NONVOLATILE TRANSISTOR PAIRS WITH SHARED CONTROL GATE 审中-公开
标题翻译：用于生产非易失性晶体管对方法的共享控制栅极
公开(公告)号：EP1665356A2
公开(公告)日：2006-06-07
申请号：EP04782838.9
申请日：2004-09-01
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： A pair of nonvolatile memory transistors are carved from a single polysilicon floating gate (23) on an insulated substrate (11). After surrounding the poly floating gate with insulator, the poly is etched except for two remnants (21a, 21b) remaining on lateral sides of the original floating gate. These remnants become a pair of new floating gates for the transistor pair. Prior to etching of the poly (23), the poly may be used for self-aligned placement of highly doped regions (35, 37) that serve as electrodes for the two transistors. If the single poly floating gate has a minimum feature size for a manufacturing process, the pair of poly remnants (21a, 21b) remaining after etching are even smaller, perhaps less than a fraction of the minimum feature size. With this small size, the devices will operate by band-to-band tunneling, i.e. without tunnel oxide, characteristic of larger EEPROM and EPROM devices. A single conductive control electrode (53) over the poly remnants can allow both transistors to operate as independent storage devices if bit lines (83, 85), connected to other electrodes, are phased.

5. 发明公开

EP1652236A1 EEPROM WITH MULTI-MEMBER FLOATING GATE 审中-公开
标题翻译：随着越来越多的LINK-浮栅EEPROM
公开(公告)号：EP1652236A1
公开(公告)日：2006-05-03
申请号：EP04778855.9
申请日：2004-07-21
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An EEPROM device constructed in a first active area (21) having a multi-element floating gate structure, including a central polysilicon body (51) surrounded by a polysilicon spacer element (69) and mutually separated by an upright layer (63) of thin oxide (61) for electron tunneling. An auxiliary active area (23), isolated from the first active area, is employed as a charge reservoir for programming and linked to the first active area by an extended ion implantation region (45). A poly cap (99) makes contact with the poly spacer (69) but not the central poly body (51). A hole (82), made through the poly cap and into the central poly body, is then filled with metal (91), electrically joining the poly cap and the connected poly spacer with the central poly body.

6. 发明公开

EP1535325A1 METHOD OF PREVENTING SHIFT OF ALIGNMENT MARKS DURING RAPID THERMAL PROCESSING 审中-公开
标题翻译：程序防止校准标记在运动过程中快速热处理
公开(公告)号：EP1535325A1
公开(公告)日：2005-06-01
申请号：EP03734353.0
申请日：2003-06-02
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil , WHITEMAN, Michael, D.
IPC分类号： H01L21/76
CPC分类号： H01L21/26513 , H01L21/2652 , H01L21/324 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for preventing thermal stress and the shifting of alignment marks during semiconductor processing including providing a semiconductor wafer (10) having a first selected portion (12) for fabricating integrated circuitry and a second non-fabrication portion (14) including alignment marks (16), introducing dopant (56) into said first and second portions, when dopant (56) is required to be introduced in said first portion (12), thereby increasing radiant energy absorptivity and decreasing radiant energy transmissivity in both portions (12, 14) such that the thermal emissions detected at the portions result in no significant temperature variation between portions during heating. Therefore thermal stress and shifting of alignment marks (16) are prevented.

7. 发明公开

EP1766671A1 METHOD OF MAKING MIRROR IMAGE MEMORY CELL TRANSISTOR PAIRS FEATURING POLY FLOATING SPACES 审中-公开
标题翻译：用于生产镜像存储单元晶体管对和POLYFLOATING，空间
公开(公告)号：EP1766671A1
公开(公告)日：2007-03-28
申请号：EP05761992.6
申请日：2005-06-16
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L21/3205 , H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883 , H01L29/7887
摘要： By arranging floating spacer and gate nonvolatile memory transistors (Fig. 1) in symmetric (30) pairs, increased chip density may be attained. For each pair of such transistors, the floating gates (17a, 17b) are laterally aligned with floating spacers (45, 47) appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common electrode (57). The transistors are independent of each other except for the shared electrode. Tunnel oxide (41) separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charged is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.

8. 发明公开

EP1721321A2 NON-VOLATILE MEMORY ARRAY WITH SIMULTANEOUS WRITE AND ERASE FEATURE 审中-公开
标题翻译：与同时写入特征并删除不挥发存储器矩阵
公开(公告)号：EP1721321A2
公开(公告)日：2006-11-15
申请号：EP05712842.3
申请日：2005-01-27
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： G11C11/34
CPC分类号： G11C16/102 , G11C16/14
摘要： A non-volatile transistor memory array has individual cells with a current injector (21) and a non-volatile memory transistor (23). Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line (19, 102), the active row has current injectors (21) ready to operate if program line (11, 13) voltages are appropriate to cause charge storage in a memory cell (23), while a cell in an adjacent row be erased by charge being driven from a memory transistor. A series of conductive plates (30) are arranged over the word line (19), with each plate having a pair of oppositely extending tangs (86, 88), one causing programming of a cell in a first row and another causing erasing of a cell in another row.

9. 发明公开

EP1576668A1 MULTI-LEVEL MEMORY CELL WITH LATERAL FLOATING SPACERS 审中-公开
标题翻译：具有横向浮动空间的多级存储器单元
公开(公告)号：EP1576668A1
公开(公告)日：2005-09-21
申请号：EP03814101.6
申请日：2003-12-18
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil
IPC分类号： H01L27/108 , H01L29/788 , H01L29/76
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/7887
摘要： A multi-level non-volatile memory transistor (33) is formed in a semiconductor substrate (57). A conductive polysilicon control gate (51; 62) having opposed sidewalls is insulatively spaced (56) just above the substrate. Conductive polysilicon spacers (53, 55;91, 93) are separated from the opposed sidewalls by thin tunnel oxide (59; 74). Source and drain implants (61, 63; 101, 103) are beneath or slightly outboard of the spacers. Insulative material (104, 109) is placed over the structure with a hole (125) cut above the control gate for contact by a gate electrode (127) connected to, or part of, a conductive word line. Auxiliary low voltage transistors (23-26) which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses((~1, p2) to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then t he other side.
摘要翻译：多级非易失性存储晶体管（33）形成在半导体衬底（57）中。具有相对侧壁的导电多晶硅控制栅极（51; 62）在衬底正上方绝缘间隔（56）。导电多晶硅间隔物（53,55; 91,93）通过薄隧道氧化物（59; 74）与相对的侧壁分开。源极和漏极植入物（61,63; 101,103）位于间隔物之下或略微外侧。绝缘材料（104,109）被放置在结构上方，在控制栅极上方切出一个孔（125），用于通过连接到导电字线或部分导电字线的栅电极（127）进行接触。辅助低电压晶体管（23-26）可以在形成存储器晶体管的同时形成，向源极和漏极施加反相时钟脉冲（（〜1，p2），使得存储晶体管的第一侧可能会被写入或阅读，然后他的另一边。

10. 发明公开

EP1340264A1 SELF-ALIGNED NON-VOLATILE MEMORY CELL 审中-公开
标题翻译： SELF调谐非易失性存储装置
公开(公告)号：EP1340264A1
公开(公告)日：2003-09-03
申请号：EP01983134.6
申请日：2001-10-15
申请人： ATMEL CORPORATION
发明人： LOJEK, Bohumil , RENNINGER, Alan, L.
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/76895 , H01L29/42324 , H01L29/42328 , H01L29/7883
摘要： Disclosed is a self-aligned non-volatile memory cell (200) comprising a small sidewall spacer (239) electrically coupled and being located next to a main floating gate region (212). Both the small sidewall spacer (239) and the main floating gate region (212) are formed on a substrate (204) and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer (232) which is thinner (260) between the small sidewall spacer (239) and the substrate (204); and is thicker (263) between the main floating gate region (212) and the substrate (204). The small sidewall spacer (239) can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

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