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1. 发明公开

EP0331206A2 Semiconductor integrated circuit device of multilayer interconnection structure 失效
标题翻译： Integrierte Schaltungshalbleiteranordnung mit Mehrschicht-Verbindungsstruktur。
公开(公告)号：EP0331206A2
公开(公告)日：1989-09-06
申请号：EP89103926.5
申请日：1989-03-06
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kato, Toshiya , Enkaku, Motohiro
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/5286 , H01L23/5226 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A semiconductor integrated circuit device of multilayer interconnection structure includes a pad (34) formed of a multilayer interconnection layer (52, 54). The power source pad (34) is connected to a power source interconnection layer (33) via a lead-out interconnection layer (35) which is formed of the same multilayer interconnection layer (52, 54) as that used to form the power source pad (34).
摘要翻译：多层互连结构的半导体集成电路器件包括由多层互连层（52,54）形成的焊盘（34）。电源焊盘（34）经由引出互连层（35）连接到电源互连层（33），引出互连层（35）由与用于形成电源的相同的多层互连层（52,54）形成垫（34）。

2. 发明公开

EP0331206A3 Semiconductor integrated circuit device of multilayer interconnection structure 失效
标题翻译：多层互连结构半导体集成电路设备
公开(公告)号：EP0331206A3
公开(公告)日：1991-05-02
申请号：EP89103926.5
申请日：1989-03-06
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Kato, Toshiya , Enkaku, Motohiro
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/5286 , H01L23/5226 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A semiconductor integrated circuit device of multilayer interconnection structure includes a pad (34) formed of a multilayer interconnection layer (52, 54). The power source pad (34) is connected to a power source interconnection layer (33) via a lead-out interconnection layer (35) which is formed of the same multilayer interconnection layer (52, 54) as that used to form the power source pad (34).

3. 发明公开

EP0307722A1 Semiconductor device having improved multilayered wirings 失效
标题翻译： Halbleiteranordnung mit Mehrschichtleiter。
公开(公告)号：EP0307722A1
公开(公告)日：1989-03-22
申请号：EP88114229.3
申请日：1988-08-31
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Enkaku, Motohiro c/o Patent Division , Kato, Toshiya
IPC分类号： H01L23/52
CPC分类号： H01L23/5384 , H01L23/528 , H01L23/5286 , H01L24/06 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device includes a circuit block (11) formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern (12) formed in a first layer of the multilayered wiring layers and running around the circuit block (11), a second current path pattern (13) formed in a second layer of the multilayered wiring layers and running around the circuit block (11), part of the second current path pattern (13) lying over the first current path pattern (12) and the other portion of the second current path pattern (13) lying off the first current path pattern (12) so as to define a connection space with a predetermined width (X) between the first current path pattern (12) and the second current path pattern (13), a first signal path pattern (14A) formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block (11), a second signal path pattern (14B) formed in the second layer of the multilayered wiring layers and serving as the signal path to the circuit block (11), and a via contact (15), formed in the connection space, for electrically coupling the first signal path pattern (14A) and the second signal path pattern (14B).
摘要翻译：一种半导体器件，包括形成在具有两层或更多层并具有特定功能的多层布线层的半导体芯片上的电路块（11），形成在多层布线的第一层中的第一电流路径图案并且围绕电路块（11）运行，形成在多层布线层的第二层中并围绕电路块（11）运行的第二电流路径图案（13），位于第二电流路径图案（13）的部分位于在所述第一电流路径图案（12）之上并且所述第二电流路径图案（13）的位于所述第一电流路径图案（12）之外的另一部分以限定所述第一电流路径图案（12）之间的预定宽度（X）的连接空间路径图案（12）和第二电流路径图案（13），形成在多层布线层的第一层中并用作到电路块（11）的信号路径的第一信号路径图案（14A），第二信号路径图案（14B）形成在所述多层布线层的第二层中并且用作到所述电路块（11）的信号路径;以及形成在所述连接空间中的用于将所述第一信号路径图案（14A）和第二信号路径图案（14B）。

4. 发明授权

EP0307722B1 Semiconductor device having improved multilayered wirings 失效
标题翻译：具有改进的多层布线的半导体器件
公开(公告)号：EP0307722B1
公开(公告)日：1993-03-17
申请号：EP88114229.3
申请日：1988-08-31
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Enkaku, Motohiro c/o Patent Division , Kato, Toshiya
IPC分类号： H01L23/52
CPC分类号： H01L23/5384 , H01L23/528 , H01L23/5286 , H01L24/06 , H01L2924/14 , H01L2924/00

5. 发明公开

EP0464667A3 Power-on-clear signal generating circuit 失效
标题翻译：上电清除信号发生电路
公开(公告)号：EP0464667A3
公开(公告)日：1992-04-22
申请号：EP91110651.6
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Hashimoto, Hisashi, c/o Intellectual , Kato, Toshiya
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： The gate of an enhancement type N-channel MOS transistor (23) is connected to the drain of a P-channel MOS transistor (22), which serves as a load element. The source and drain of the N-channel MOS transistor (23) is connected to the ground voltage GND. The input terminal of a Schmitt trigger circuit (25) is the connection node which connects the drain of the P-channel MOS transistor (22) and the gate of the N-channel MOS transistor (23) to each other. The output terminal (26) from which a power-on-clear signal (POC) is output is connected to the output terminal of the Schmitt trigger circuit (25).

6. 发明公开

EP0464667A2 Power-on-clear signal generating circuit 失效
标题翻译： Schaltung zum Erzeugen einesEinschaltrücksetzsignals。
公开(公告)号：EP0464667A2
公开(公告)日：1992-01-08
申请号：EP91110651.6
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Hashimoto, Hisashi, c/o Intellectual , Kato, Toshiya
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： The gate of an enhancement type N-channel MOS transistor (23) is connected to the drain of a P-channel MOS transistor (22), which serves as a load element. The source and drain of the N-channel MOS transistor (23) is connected to the ground voltage GND. The input terminal of a Schmitt trigger circuit (25) is the connection node which connects the drain of the P-channel MOS transistor (22) and the gate of the N-channel MOS transistor (23) to each other. The output terminal (26) from which a power-on-clear signal (POC) is output is connected to the output terminal of the Schmitt trigger circuit (25).
摘要翻译：增强型N沟道MOS晶体管（23）的栅极连接到用作负载元件的P沟道MOS晶体管（22）的漏极。 N沟道MOS晶体管（23）的源极和漏极连接到地电压GND。施密特触发电路（25）的输入端是将P沟道MOS晶体管（22）的漏极和N沟道MOS晶体管（23）的栅极彼此连接的连接节点。输出电源接通清除信号（POC）的输出端子（26）连接到施密特触发电路（25）的输出端子。

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