专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0437307A3 High resistance polysilicon load resistor 失效
标题翻译：高电阻多晶硅负载电阻
公开(公告)号：EP0437307A3
公开(公告)日：1991-10-30
申请号：EP91300026.1
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L27/11 , H01L21/82 , H01L21/3205
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

2. 发明公开

EP0437306A2 Self-aligning contact and interconnect structure 失效
标题翻译： Selbstjustierender Kontakt und Verbindungsstrukturen。
公开(公告)号：EP0437306A2
公开(公告)日：1991-07-17
申请号：EP91300024.6
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/90 , H01L23/485
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density.
Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.
摘要翻译：用于集成电路的MOS晶体管，特别是CMOS集成电路，其制造具有允许更高封装密度的自对准接触和互连结构。自对准源极和漏极触点与栅极重叠，但是通过源极/漏极接触和栅极之间的氧化物绝缘以及栅极上方的氮化硅层来防止与栅极的短路。在晶体管的有源区域上在栅极的顶部形成与栅极的触点，因为源极和漏极区域在蚀刻绝缘体以暴露栅极触点期间被硬化的光致抗蚀剂层保护。源极，漏极和栅极触点由一层硅化钛保护，使得互连不需要完全覆盖这些区域。低电阻互连由氮化钛薄膜包围的硅化钛形成。

3. 发明公开

EP0437307A2 High resistance polysilicon load resistor 失效
标题翻译： Polysilizlastwiderstand mit hohem Widerstand。
公开(公告)号：EP0437307A2
公开(公告)日：1991-07-17
申请号：EP91300026.1
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L27/11 , H01L21/82 , H01L21/3205
CPC分类号： H01L21/82 , H01L27/1112 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.
摘要翻译：用于半导体集成电路的负载电阻器由导电材料的两部分组成，通常形成在半导体衬底上并分离了一定距离的硅化物或复合多晶硅层和形成在其上的硅化物层的条带。在导电材料的第一和第二部分上形成导电掺杂剂扩散阻挡层。然后将多晶硅材料放置在结构上，使得多晶硅材料的一部分通过扩散阻挡层与导电材料的第一部分欧姆接触，并且多晶硅材料的另一部分通过扩散与欧姆接触阻挡导电材料的第二部分。通常，多晶硅材料被放置在形成在半导体衬底上的导电材料的两部分之间的衬底部分中的绝缘层上。扩散阻挡层防止导电材料中的任何掺杂剂扩散到多晶硅材料中，从而允许多晶硅材料用作千兆欧范围内具有高电阻的负载电阻器。结构的随后的高温处理不会改变多晶硅的电阻，因为掺杂剂扩散阻挡层阻止来自下面的导电材料的任何掺杂剂扩散到多晶硅材料中。

4. 发明公开

EP0437306A3 Self-aligning contact and interconnect structure 失效
标题翻译：自对准接触和互连结构
公开(公告)号：EP0437306A3
公开(公告)日：1993-03-31
申请号：EP91300024.6
申请日：1991-01-02
申请人： PARADIGM TECHNOLOGY, INC.
发明人： Godinho, Norman , Lee, Frank Tsu-Wei , Chen, Hsiang-Wen , Motta, Richard F. , Tsang, Juine-Kai , Tzou, Joseph , Baik, Jai-Man , Yen, Ting-Pwu
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/90 , H01L23/485
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823864 , H01L21/823871 , H01L23/53257 , H01L23/53271 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式