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81. 发明授权

EP1546868B1 SUPERPIPELINED VLIW PROCESSOR ADDRESSING BYPASS-LOOP SPEED LIMITATION 有权
标题翻译：超级管道，VLIW处理器速度限制的治疗由于旁路回路
公开(公告)号：EP1546868B1
公开(公告)日：2008-11-19
申请号：EP03756845.8
申请日：2003-09-17
申请人： NXP B.V.
发明人： SLAVENBURG, Gerrit , VAN DE WAERDT, Jan-Willem
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3875 , G06F9/3824 , G06F9/3826 , G06F9/3885 , G06F9/3891

82. 发明公开

EP1891516A2 SYSTEM AND METHOD FOR POWER SAVING IN PIPELINED MICROPROCESSORS 审中-公开
标题翻译：用于管道式微处理器中的节能的系统和方法
公开(公告)号：EP1891516A2
公开(公告)日：2008-02-27
申请号：EP06760325.8
申请日：2006-05-24
申请人： Atmel Corporation
发明人： RENNO, Erik, K. , STROM, Oyvind
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/3824 , G06F9/3826
摘要： A system and method for preserving power in a microprocessor pipeline (300). The system includes a register file read control unit (305), the read control unit (305) being configured to monitor one or more outputs from a control /decode unit (205) of the pipeline (300) and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units (301, 303) each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units (301, 303) being coupled to a unique register port of a register file (109) within the pipeline (300). The input of each of the one or more read inhibit units (301, 303) being coupled to the control/decode unit (205), and the enable terminal of each of the one or more read inhibit units (301, 303) being coupled to a unique output of the read control unit (305).
摘要翻译：一种用于在微处理器管线（300）中保存功率的系统和方法。该系统包括寄存器文件读取控制单元（305），读取控制单元（305）被配置为监测来自流水线（300）的控制/解码单元（205）的一个或多个输出并且监视来自一个或多个管道的更多其他阶段。该系统还包括一个或多个读取禁止单元（301,303），每个读取禁止单元具有输入，输出和使能端子，一个或多个读取禁止单元（301,303）中的每一个的输出耦合到唯一的寄存器管道（300）内的寄存器文件（109）的端口。一个或多个读取禁止单元（301,303）中的每一个的输入端耦合到控制/解码单元（205），并且一个或多个读取禁止单元（301,303）中的每一个的使能端被耦合到读取控制单元（305）的唯一输出。

83. 发明公开

EP1883075A1 Content-addressable memory that supports a priority ordering between banks 审中-公开
标题翻译： Inhaltsadressierbarer Speicher，der eine Priorisierung zwischen Bankenunterstützt
公开(公告)号：EP1883075A1
公开(公告)日：2008-01-30
申请号：EP07252907.6
申请日：2007-07-23
申请人： SUN MICROSYSTEMS, INC.
发明人： Cypher, Robert E.
IPC分类号： G11C15/00 , G06F12/08
CPC分类号： G11C15/04 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F12/0864
摘要： One embodiment of the present invention provides a system that implements a content-addressable memory (CAM) which has multiple banks. During operation, the system receives a request to insert an item into the CAM, wherein the request includes a key which is used to index the item and a body containing data. Next, for each bank in the CAM, the system calculates a different hash function based on the key to produce an index and a tag. The system then uses the calculated index and the tag for each bank to lookup an entry in each bank. If the lookups do not generate a hit in any bank, the system stores an entry for the request into a highest priority bank which does not contain a valid entry in the location accessed by the lookup. In one embodiment of the present invention, the multiple banks in the CAM have varying sizes.
摘要翻译：本发明的一个实施例提供一种实现具有多个存储体的内容寻址存储器（CAM）的系统。在操作期间，系统接收将项目插入CAM中的请求，其中该请求包括用于索引项目的密钥和包含数据的主体。接下来，对于CAM中的每个存储体，系统基于该键计算不同的散列函数以产生索引和标签。然后，系统使用计算的索引和每个银行的标签来查找每个银行中的条目。如果查找不在任何存储区中产生命中，则系统将该请求的条目存储到最高优先级的存储库中，该存储体在查找访问的位置中不包含有效条目。在本发明的一个实施例中，CAM中的多个组具有不同的大小。

84. 发明授权

EP1116103B1 MECHANISM FOR STORE-TO-LOAD FORWARDING 有权
标题翻译：机理“店里加载转送”
公开(公告)号：EP1116103B1
公开(公告)日：2006-06-21
申请号：EP99916331.4
申请日：1999-04-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WITT, David, B.
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A load/store unit (42) searches a store queue (64) included therein for each byte accessed by the load independently from the other bytes, and determines the most recent store (in program order) to update that byte. Accordingly, even if one or more bytes accessed by the load are modified by one store while one or more other bytes accessed by the load are modified by another store, the forwarding mechanism may assemble the bytes accessed by the load. More particularly, load data may be forwarded accurately from an arbitrary number of stores. In other words, forwarding may occur up to N stores (where N is the number of bytes accessed by the load). In one particular embodiment, the load/store unit (42) generates a bit vector from a predetermined set of least significant bits of the addresses of loads and stores. The bit vector includes a bit for each byte in a range defined by the number of least significant bits. The bit indicates whether or not the byte is updated (for store bit vectors) or accessed (for load bit vectors). The load/store unit (42) may then examine the bit vectors (and compare the remaining bits of the store and load addresses, exclusive of the least significant bits used to generate the bit vectors) in order to locate the most recent update of each byte.

85. 发明公开

EP1658559A2 INSTRUCTION CONTROLLED DATA PROCESSING DEVICE 有权转让
标题翻译：路线指南控制的数据处理设备和方法
公开(公告)号：EP1658559A2
公开(公告)日：2006-05-24
申请号：EP04744376.7
申请日：2004-06-22
申请人： Koninklijke Philips Electronics N.V.
发明人： ALBA PINTO, Carlos, A. , SRINIVASAN, Balakrishnan , SETHURAMAN, Ramanathan
IPC分类号： G06F9/318 , G06F9/38 , G06F1/32 , G06F9/30 , G06F9/34
CPC分类号： G06F9/3826 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F9/3824 , G06F9/3836 , G06F9/3853 , G06F9/3869 , G06F9/3885 , Y02D10/126 , Y02D10/152
摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

86. 发明公开

EP1220092A3 System and method for executing variable latency load operations in a data processor 有权
标题翻译：系统和方法，用于执行加载操作可变等待时间
公开(公告)号：EP1220092A3
公开(公告)日：2006-04-26
申请号：EP01310645.5
申请日：2001-12-19
申请人： STMicroelectronics, Inc.
发明人： Jarvis, Anthony X. , Faraboschi, Paolo
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3885 , G06F9/3891 , G06F12/0855
摘要： There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages for performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of registers for receiving the data values from the data cache; 4) a load store unit for transferring a first one of the data values from the data cache to a target one of the plurality of registers during execution of a load operation; 5) a shifter circuit associated with the load store unit for shifting the first data value prior to loading the first data value into the target register; and 6) bypass circuitry associated with the load store unit for transferring the first data value from the data cache directly to the target register without processing the first data value in the shifter circuit.

87. 发明公开

EP1442362A1 AN ARRANGEMENT AND A METHOD IN PROCESSOR TECHNOLOGY 审中-公开
标题翻译：安排与方法在处理器技术
公开(公告)号：EP1442362A1
公开(公告)日：2004-08-04
申请号：EP01977045.2
申请日：2001-10-24
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： LINNERMARK, Nils, Ola
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/30101 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A processor (PR2) has a functional unit (FU21) connected to series coupled temporary registers (TR21-TR23) and to a register file (RF2), which has an output connected to an input (IP1) of the functional unit via multiplexors (MUX1-MUX4). Read addresses (B, E, A) and write addresses (A, D, G) are sent to the register file and to a control means. The latter includes registers (REG1-REG4) and comparators (C1-C4) which control the multiplexors (MUX1-MUX4). On a read address (B) a value (V(B)) is sent to the functional unit (FU21) after the register file access time has lapsed. The functional unit performs an operation and the result (V(A)) is clocked through the temporary registers (TR1-TR3) and is sent to the register file (RF2). A later read address (A) coincides in the comparator (C2) with a write address (A) from the register (REG2), the multiplexer (MUX2) is switched and the result (V(A)) is fetched from the temporary register (TR1). The result (V(A)) can already be used, although it is under access in the register file (RF2) and can not yet be fetched from there.

88. 发明公开

EP1296228A2 Instruction Issue and retirement in processor having mismatched pipeline depths 有权
标题翻译： Ausgabe und Abschluss von Befehlen在einem Prozessor mit unterchiedlicher Pipelinetiefe
公开(公告)号：EP1296228A2
公开(公告)日：2003-03-26
申请号：EP02021392.2
申请日：2002-09-24
申请人： Broadcom Corporation
发明人： Yeh, Tse-Yu , Kruckemyer, David A. , Rogenmoser, Robert
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/3806 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3863 , G06F9/3867 , G06F9/3873
摘要： A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.
摘要翻译：描述了包括第一管线，第二管线和控制电路的处理器。第一条流水线包括第一阶段，指令结果承诺到架构状态。第一阶段与第一批管道的问题阶段分开第一阶段。第二流水线包括第二阶段，在该第二阶段可以报告异常，其中第二阶段与第二流水线的问题阶段分离大于第一数量的第二阶段。如果第一指令在程序顺序中在第二指令之后，则控制电路被配置为禁止向第一流水线共同发出第一指令，并且向第二流水线发送第二指令。

89. 发明公开

EP1208424A2 APPARATUS AND METHOD FOR REDUCING REGISTER WRITE TRAFFIC IN PROCESSORS WITH EXCEPTION ROUTINES 有权
标题翻译：设备和方法减少了数据写入流量在处理器中EXCEPT例程
公开(公告)号：EP1208424A2
公开(公告)日：2002-05-29
申请号：EP01953031.0
申请日：2001-01-24
申请人： Koninklijke Philips Electronics N.V.
发明人： STRAVERS, Paul
IPC分类号： G06F9/00
CPC分类号： G06F9/3867 , G06F9/3826 , G06F9/3861
摘要： An instruction execution device and method are disclosed for reducing register write traffic within a processor with exception routines. The instruction execution device includes an instruction pipeline for producing a result for an instruction, wherein the exception routines may interrupt the instruction pipeline a random intervals, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction, a First in First out (FIFO) buffer for storing the result and a FIFO control for writing the contents of the FIFO buffer to the register file when an exception occurs.

90. 发明公开

EP1137984A2 A MULTIPLE-THREAD PROCESSOR FOR THREADED SOFTWARE APPLICATIONS 有权
标题翻译： MUCH线程处理器线程软件应用
公开(公告)号：EP1137984A2
公开(公告)日：2001-10-04
申请号：EP99963017.1
申请日：1999-12-03
申请人： Sun Microsystems, Inc.
发明人： TREMBLAY, Marc , JOY, William, N.
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/3001 , G06F9/3012 , G06F9/30123 , G06F9/3824 , G06F9/3851 , G06F9/3877
摘要： A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent parallel execution paths include functional units that execute an instruction set including special data-handling instructions that are advantageous in a multiple-thread environment.

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