专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明公开

EP0390522A3 Bipolar transistor and photoelectric conversion apparatus using the same 失效
标题翻译：双极晶体管和光电转换装置
公开(公告)号：EP0390522A3
公开(公告)日：1990-11-14
申请号：EP90303286.0
申请日：1990-03-28
申请人： CANON KABUSHIKI KAISHA
发明人： Morishita, Masakazu
IPC分类号： H01L29/08 , H01L29/161 , H01L29/165 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L27/14681 , H01L29/161 , H01L29/165 , H01L29/36 , H01L29/7375 , H01L31/1105
摘要： A semiconductor device comprises an emitter of first conductivity type, a base of second conductivity type, and a collector of first conductivity type. At least a vicinity of an interface of the emitter to base junction is formed by Si. Polycrystalline or single crystalline Si 1-x C x (x ≦ 0.5) is formed on a region formed by the Si of said emitter. A junction between a region of the Si and a region of the polycrystalline and the single crystalline Si 1-x C x is a graded hetero junction.

72. 发明公开

EP0161556A3 Integrated circuit compatible thin film field effect transistor and method of making same 失效
标题翻译：集成电路兼容薄膜场效应晶体管及其制作方法
公开(公告)号：EP0161556A3
公开(公告)日：1987-08-19
申请号：EP85105035
申请日：1985-04-25
申请人： ENERGY CONVERSION DEVICES, INC.
发明人： Ovshinsky, Stanford R. , Hudgens, Stephen J.
IPC分类号： H01L29/78 , H01L29/04 , H01L29/56 , H01L21/84 , H01L21/324
CPC分类号： H01L27/1214 , H01L21/324 , H01L29/04 , H01L29/161 , H01L29/66742 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： There is disclosed integrated circuit compatible thin film field effect transistors which can be fabricated at low temperatures and operated at fast switching rates for use, for example, in video rate applications. The transistors include a silicon-germanium alloy body having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistors are rectifying contacts formed on or in the body. Also disclosed are a method of making the transistors and an electronically addressable array system utilizing the transistors to advantage.
摘要翻译：公开了集成电路兼容的薄膜场效应晶体管，其可以在低温下制造并且以快速切换速率操作以用于例如视频速率应用。晶体管包括硅 - 锗合金体，其具有比无定形材料更有序的结构，并且比单晶材料有序。晶体管的源极和漏极是形成在体内或体内的整流触点。还公开了制造晶体管和利用晶体管的电子可寻址阵列系统的方法。

73. 发明授权

EP3859769B1 PROCEDE DE GRAVURE A L'ECHELLE NANOMETRIQUE D'UN ALLIAGE GERMANIUM ETAIN (GESN) POUR TRANSISTOR A EFFET DE CHAMP 有权
公开(公告)号：EP3859769B1
公开(公告)日：2024-06-26
申请号：EP21153243.7
申请日：2021-01-25
IPC分类号： H01L21/3065 , H01L29/78 , H01L29/06 , B82Y10/00 , H01L29/161 , H01L29/66 , H01L29/739 , H01L29/775 , H01L29/786
CPC分类号： H01L21/3065 , H01L29/775 , H01L29/0673 , H01L29/0676 , H01L29/161 , H01L29/7391 , H01L29/66439 , H01L29/66356 , B82Y10/00 , H01L29/78684

74. 发明公开

EP4386851A1 EPITAXIAL SOURCE OR DRAIN REGION WITH A WRAPPED CONDUCTIVE CONTACT 审中-公开
公开(公告)号：EP4386851A1
公开(公告)日：2024-06-19
申请号：EP23200754.2
申请日：2023-09-29
申请人： INTEL Corporation
发明人： JUN, Hwichan
IPC分类号： H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/10 , H01L29/161
CPC分类号： H01L29/0847 , H01L29/0673 , H01L29/41725 , H01L29/161 , B82Y10/00 , H01L29/66439 , H01L29/775 , H01L29/1079 , H01L29/42392 , H01L29/66545 , H01L21/28518
摘要： Techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. The first and second semiconductor devices include a subfin region adjacent to a dielectric layer. A conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. A dielectric layer is also present between the conductive contact and the subfin region.

75. 发明公开

EP4383341A2 NANOSHEET SEMICONDUCTOR DEVICE COMPRISING A MULTILAYER SOURCE/DRAIN REGION 审中-实审
公开(公告)号：EP4383341A2
公开(公告)日：2024-06-12
申请号：EP23192937.3
申请日：2023-08-23
申请人： Samsung Electronics Co., Ltd.
发明人： SHIN, Dong Suk , KIM, Jung Taek , YU, Hyun-Kwan , KIM, Seok Hoon , PARK, Pan Kwi , JEONG, Seo Jin , CHO, Nam Kyu
IPC分类号： H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/201 , B82Y10/00 , H01L29/78 , H01L27/088
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/41766 , H01L29/7848 , H01L29/42392 , H01L29/201 , H01L27/088
摘要： There is provided a semiconductor device, preferably a nanosheet field-effect transistor, capable of improving performance and reliability of an element. The semiconductor device includes an active pattern (NS1) extending in a first direction, (D1) and a plurality of gate structures (INT_GS1) spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode (120) extending in a second direction and a gate spacer (GS1, 140) on a sidewall of the gate electrode and a source/drain pattern (150, 151, 152) disposed between adjacent gate structures. The source/drain structure comprises a semiconductor liner layer (151) and a semiconductor filling layer (152) on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion (152UP) protruding in a third direction beyond an upper surface of the active pattern (NS1). A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction at the vertical position of the upper surface of the active pattern (NS1). Furthermore, in a plan view (Fig. 5), the inner surface of the semiconductor liner layer comprises a concave region.

76. 发明公开

EP3252827A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP3252827A1
公开(公告)日：2017-12-06
申请号：EP17173729.9
申请日：2017-05-31
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZHOU, Fei
IPC分类号： H01L29/66 , H01L29/78 , H01L27/092
CPC分类号： H01L27/0924 , H01L21/0332 , H01L21/0337 , H01L21/28035 , H01L21/31111 , H01L21/31144 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L27/0922 , H01L29/0649 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/4916 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present invention provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device.
摘要翻译：本发明提供了一种半导体器件及其制造方法。该器件可以包括：半导体衬底; 从半导体衬底突出的鳍片，其中沟槽形成在鳍片的侧面上; 部分地填充沟槽的第一绝缘体层，其中鳍状物从第一绝缘体层突出; 覆盖所述鳍状物的第二绝缘体层; 在所述第二绝缘层上的多个伪栅极结构，其中每个伪栅极结构包裹所述鳍的一部分，其中每个伪栅极结构包括位于所述第二绝缘层上的伪栅极，所述多个伪栅极结构包括至少一个第一伪栅极结构和第二伪栅极结构，所述第二伪栅极结构位于所述鳍片的边角，所述第二伪栅极结构的一部分位于所述第一绝缘层上; 在所述多个伪栅极结构中的每一个的两侧处的所述第一绝缘体层和所述第二绝缘体层上的间隔体; 以及位于多个伪栅极结构之间的源极或漏极。本发明可以提高设备的可靠性。

77. 发明公开

EP3252826A1 METHOD AND DEVICE FOR COMPOUND SEMICONDUCTOR FIN STRUCTURE 审中-公开
标题翻译：用于复合半导体鳍结构的方法和装置
公开(公告)号：EP3252826A1
公开(公告)日：2017-12-06
申请号：EP17173727.3
申请日：2017-05-31
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZHANG, Hai Yang , WANG, Yan
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/3065 , H01L29/0649 , H01L29/1033 , H01L29/161 , H01L29/20 , H01L29/66522 , H01L29/6653 , H01L29/66553 , H01L29/66787 , H01L29/785
摘要： A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成第一半导体层;在第一半导体层上形成半导体层结构的堆叠;以及刻蚀堆叠以形成鳍状结构。每个半导体层结构包括在第一绝缘层上的第一绝缘层和第二半导体层。第一和第二半导体层具有相同的半导体化合物。根据新颖方法的鳍状结构包括一个或多个绝缘体层以实现较高的电流/关断电流比，由此相对于没有绝缘体层的传统鳍结构提高了器件性能。

78. 发明公开

EP3087603A4 HIGH MOBILITY TRANSISTORS 审中-公开
标题翻译： TRANSISTOREN MIT HOHERMOBILITÄT
公开(公告)号：EP3087603A4
公开(公告)日：2017-08-30
申请号：EP14875258
申请日：2014-12-29
申请人： TEXAS INSTRUMENTS INC
发明人： NIIMI HIROAKI , MEHROTRA MANOJ , WISE RICK L
IPC分类号： H01L27/092 , B82Y40/00 , H01L21/8238 , H01L29/10
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/20
摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.
摘要翻译：包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有电介质层。 finFET的鳍具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍片位于穿过衬底上的介电层的第一沟槽中的第一硅锗缓冲器上。 p沟道finFET的鳍片位于穿过衬底上的电介质层的第二沟槽中的第二硅锗缓冲器上。鳍片在介电层上延伸至少10纳米。通过在电介质层中的沟槽中的硅锗缓冲器上外延生长来形成鳍，接着进行CMP平坦化直到电介质层。介电层凹陷以暴露鳍片。翅片可以同时形成或分开形成。

79. 发明公开

EP3087616A4 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURES ON DISSIMILAR SUBSTRATES 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG VON HALBLEITERSTRUKTUREN AUF UNGLEICHEN SUBSTRATEN
公开(公告)号：EP3087616A4
公开(公告)日：2017-08-02
申请号：EP13900449
申请日：2013-12-23
申请人： INTEL CORP
发明人： CHU-KUNG BENJAMIN , TAFT SHERRY R , LE VAN H , DASGUPTA SANSAPTAK , SUNG SEUNG HOON HOON , GARDNER SANAZ K , METZ MATTHEW V , RADOSAVLJEVIC MARKO , THEN HAN WUI
IPC分类号： H01L33/00
CPC分类号： H01L29/1037 , H01L29/0649 , H01L29/161 , H01L29/2003 , H01L29/66795
摘要： Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
摘要翻译：公开了用于在具有多深宽比掩模的不同衬底上形成无缺陷半导体结构的技术。多深宽比掩模包括在衬底上形成的第一，第二和第三层。第二层具有分别比第一层和第三层中的第一开口和第三开口更宽的第二开口。所有三个开口都沿共同的中心轴居中。半导体材料从衬底的顶表面生长并横向地在第二开口内的第一层的顶表面上生长。通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内和垂直下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

80. 发明公开

EP3036769A4 IMPROVED SILICIDE FORMATION BY IMPROVED SIGE FACETING 有权
标题翻译：改进SILICIDFORMIERUNG改良SIGE小面
公开(公告)号：EP3036769A4
公开(公告)日：2017-04-12
申请号：EP14838365
申请日：2014-08-22
申请人： TEXAS INSTRUMENTS INC
发明人： EKBOTE SHASHANK S , LIM KWAN-YONG , ESHUN EBENEZER , CHOI YOUNSUNG
IPC分类号： H01L27/088 , H01L21/28 , H01L21/336 , H01L29/165
CPC分类号： H01L29/45 , H01L21/28123 , H01L21/823412 , H01L21/823425 , H01L21/823443 , H01L27/0207 , H01L27/088 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41725 , H01L29/458 , H01L29/665 , H01L29/66636 , H01L29/7848

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式