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61. 发明公开

EP1012879A2 FABRICATION METHOD FOR REDUCED-DIMENSION INTEGRATED CIRCUITS 失效
标题翻译：降维集成电路的制造方法
公开(公告)号：EP1012879A2
公开(公告)日：2000-06-28
申请号：EP98909985.8
申请日：1998-01-29
申请人： Ultratech Stepper Inc.
发明人： TALWAR, Somit , KRAMER, Karl-Josef,Apartment 17 , VERMA, Guarav , WEINER, Kurt
IPC分类号： H01L21/8238 , H01L21/225 , H01L21/265 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/2254 , H01L21/26506 , H01L21/823814 , H01L29/0847 , Y10S148/061
摘要： Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (400) and (402) (e.g., less than 100 nm) depth provides a solution to fabrication problems including (a) high thermal conduction in crystalline silicon and (b) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.
摘要翻译：将晶体硅表面层预先非晶化为超浅（400）和（402）（例如，小于100nm）深度提供了制造问题的解决方案，包括（a）晶体硅中的高导热性和（b ）由场效应晶体管的已经制造的栅极对入射激光辐射的遮蔽和衍射 - 干涉效应。过去，这些问题已经阻止了现有技术的投影气体浸没式激光掺杂被有效地用于制造包括采用100nm和更浅结技术的MOS场效应晶体管的集成电路。

62. 发明授权

EP0419898B1 Verfahren zur Erhöhung der Spannungsfestigkeit eines mehrschichtigen Halbleiterbauelements 失效
标题翻译：一种用于提高多层半导体器件的介电强度的方法，
公开(公告)号：EP0419898B1
公开(公告)日：2000-05-31
申请号：EP90117012.6
申请日：1990-09-04
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Schulze, Hans-Joachim, Dr. , Mitlehner, Heinz, Dr.
IPC分类号： H01L21/332 , H01L21/331 , H01L21/263 , H01L21/225 , H01L21/266 , H01L29/32 , H01L29/167 , H01L29/74
CPC分类号： H01L21/263 , H01L21/221

63. 发明授权

EP0594339B1 Method of manufacturing a CMOS device 失效
标题翻译：对于CMOS器件制造方法
公开(公告)号：EP0594339B1
公开(公告)日：1999-12-01
申请号：EP93308132.5
申请日：1993-10-12
申请人： NCR International, Inc. , HYUNDAI ELECTRONICS AMERICA , Symbios, Inc.
发明人： Allman, Derryl Dwayne John , Kwong, Dim-Lee
IPC分类号： H01L21/82 , H01L21/225
CPC分类号： H01L21/823814 , H01L21/2255 , H01L21/823871 , Y10S438/945

64. 发明公开

EP0936677A1 Leistungshalbleiterbauelement mit einer isolierten Gateelektrode und Verfahren zu dessen Herstellung 失效
标题翻译：具有用于其生产的绝缘栅电极和方法的功率半导体器件
公开(公告)号：EP0936677A1
公开(公告)日：1999-08-18
申请号：EP98810119.2
申请日：1998-02-16
申请人： Asea Brown Boveri AG
发明人： Bauer, Friedhelm, Dr.
IPC分类号： H01L29/78 , H01L29/739 , H01L21/225 , H01L21/331 , H01L21/336 , H01L29/417 , H01L29/06
CPC分类号： H01L29/7802 , H01L21/2257 , H01L29/0696 , H01L29/41741 , H01L29/66333 , H01L29/66712 , H01L29/7395
摘要： Es wird ein Leistungshalbleiterbauelement angegeben, bei dem die Dreischichtstruktur mit der Gateoxidschicht, der leitenden Gateelektrode und der die Gateelektrode bedeckenden Isolationsschicht bis auf die Oberfläche des Halbleitersubstrats reichende Gräben aufweist, die mit einer leitenden Polysiliziumschicht angefüllt sind. Die Polysiliziumschicht ist derart strukturiert, dass sie oberhalb der n+ Sourcegebiete n dotiert und in den übrigen Bereichen p dotiert ist.
摘要翻译：一种功率半导体器件，具有在绝缘栅电极，具有填充有多晶硅栅极沟槽（7），所有这些n掺杂局部以上在n +源区（9），并在其它区域p掺杂。一种功率半导体器件，具有在绝缘栅电极，包括：（a）掺杂以n型掺杂的半导体衬底（1）的n +多晶硅栅电极轴承栅氧化层（2）（3）和在SiO 2覆盖绝缘层（4 ）; （B）的n +源极区域中的p阱基极区域（8）; 和（c）的金属化（10）的正面和背面的基材表面上。的三层结构（2，3，4）具有向下延伸到前表面和填充有（7）具有在其他区域中的n +源区和p-掺杂上述局部n型掺杂多晶硅的沟槽，该多晶硅（7）覆盖所述三层结构，并通过正面金属化（10）覆盖。因此独立claimsoft包括生产上述功率器件的方法。

65. 发明公开

EP0834190A4 METHOD FOR SHALLOW JUNCTION FORMATION 失效
标题翻译：方法形成漏气资金跃迁
公开(公告)号：EP0834190A4
公开(公告)日：1999-07-28
申请号：EP96921048
申请日：1996-06-03
申请人： UNIV CALIFORNIA
发明人： WEINER KURT H
IPC分类号： H01L29/78 , H01L21/225 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/2257 , H01L21/823814 , Y10S148/09 , Y10S438/923
摘要： A doping sequence that reduces the cost and complexity of forming source/drain regions (11, 12) in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on glass (21), silicide contact structures (18, 19), and interference effects created by thin dielectric layers to produce source and drain junctions (23, 24) that are ultrashallow in depth but exhibit low sheet and contact resistance. The process utilizes no photolithography and can be achieved without the use of expensive vacuum equipment. The process margins are wide, and yield loss due to contact of the ultrashallow dopants is eliminated.

66. 发明公开

EP0800204A3 A process for device fabrication in which a thin layer of cobalt silicide is formed 失效
标题翻译：在其中形成薄的硅化钴为一种器件制造方法
公开(公告)号：EP0800204A3
公开(公告)日：1998-09-16
申请号：EP97302049
申请日：1997-03-25
申请人： LUCENT TECHNOLOGIES INC
发明人： TUNG RAYMOND TZUTSE
IPC分类号： H01L21/28 , H01L21/225 , H01L21/285 , H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/28518 , H01L29/41783 , H01L29/6659
摘要： The present invention is directed to a process for device fabrication in which a layer of cobalt silicide is formed as a low resistance contact layer over the source and drain regions of a device. The silicon substrate (210) is first subjected to conditions that form a thin layer of oxide (200) on the surface thereof. It is advantageous if the oxide thickness is about 0.5 nm to about 1.5 nm. At least one layer of cobalt (220) is then formed on at least the oxidized surfaces of the silicon substrate. The cobalt layer(s) is formed using conventional expedients such as e-beam evaporation. The cobalt layer(s) is formed on the substrate in an essentially oxygen free environment. Each cobalt layer has a thickness of about 1 nm to about 5 nm. While maintaining the substrate in the essentially oxygen-free environment, the substrate is annealed to form a layer of cobalt silicide (225). It is advantageous if the substrate is annealed at a temperature in the range of about 450°C to about 800°C. The cobalt silicide (225) that results has a low resistance and high uniformity that makes it advantageous for use as a contact material.

67. 发明公开

EP0803131A4 NOVEL TRANSISTOR WITH ULTRA SHALLOW TIP AND METHOD OF FABRICATION 失效
标题翻译：中性粒细胞EITER ULTRAFLACHEN ZONE UND VERFAHREN ZUR HERSTELLUNG
公开(公告)号：EP0803131A4
公开(公告)日：1998-06-17
申请号：EP95943954
申请日：1995-12-21
申请人： INTEL CORP
发明人： CHAU ROBERT S , CHERN CHAN-HONG , JAN CHIA-HONG , WELDON KEVIN R , PACKAN PAUL A , YAU LEOPOLDO D
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78 , H01L21/44 , H01L21/265 , H01L21/465 , H01L29/04 , H01L29/06 , H01L29/76
CPC分类号： H01L29/66613 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor (200) with a low resistance ultra shallow tip region (214) and its method of fabrication. The novel transistor of the present invention has a source/drain extension of tip region (210) comprising an ultra shallow region (214) which extends beneath the gate electrode and a raised region (216).
摘要翻译：具有低电阻超浅尖端区域（214）的新型晶体管（200）及其制造方法。本发明的新型晶体管具有尖端区域（210）的源极/漏极扩展部分，其包括在栅电极下方延伸的超浅区域（214）和升高区域（216）。

68. 发明公开

EP0843347A2 Method and apparatus for processing a semiconductor substrate 失效
标题翻译：用于处理半导体衬底的方法和设备
公开(公告)号：EP0843347A2
公开(公告)日：1998-05-20
申请号：EP97119819.7
申请日：1997-11-12
申请人： APPLIED MATERIALS, INC.
发明人： Sivaramakrishnan, Visweswaren , Xia, Li-Qun , Fong, Gary , Silvestre, Irwin , Shmurun, Inna , Levine, Timothy E. , Frankel, Jonathan , Nemani, Srinivas , Yieh, Ellie
IPC分类号： H01L21/316 , H01L21/225 , H01L21/76 , H01L21/762
CPC分类号： H01L21/67109 , C23C16/46 , C23C16/56 , H01L21/02129 , H01L21/02164 , H01L21/02271 , H01L21/02301 , H01L21/02315 , H01L21/0234 , H01L21/02362 , H01L21/2255 , H01L21/31604 , H01L21/31612 , H01L21/31625
摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800°C) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.
摘要翻译：本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和设备。本发明的系统，方法和设备允许在同一室内原位执行多个处理步骤以减少总处理时间并确保用于高纵横比器件的高质量处理。在同一个腔室内执行多个工艺步骤还可以增加对工艺参数的控制并减少设备损坏。特别地，本发明可以提供用于形成具有厚度均匀性，良好的间隙填充能力，高密度，低湿度和其他期望特性的介电膜的高温沉积，加热和高效清洁。

69. 发明授权

EP0451553B1 Self-aligned silicided base bipolar transistor and resistor and method of fabrication 失效
标题翻译：自Silizidbasisbipolartransistor和电阻和制造工艺
公开(公告)号：EP0451553B1
公开(公告)日：1998-05-06
申请号：EP91104215.8
申请日：1991-03-19
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： DeLong, Bancherd , Ganschow, George , Blair, Christopher Scott , Crabb, Thomas Scott
IPC分类号： H01L27/06 , H01L21/225
CPC分类号： H01L28/20 , H01L21/28525 , H01L29/66272 , H01L29/6628 , Y10S148/123

70. 发明公开

EP0813234A2 Method of manufacturing a MOSFET 失效
标题翻译： Verfahren zur Herstellung采用MOSFET
公开(公告)号：EP0813234A2
公开(公告)日：1997-12-17
申请号：EP97109395.0
申请日：1997-06-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hu, Jerry Che-Jen , Hong, Qi-Zhong , Hsia, Steve , Chen, Ih-Chin
IPC分类号： H01L21/336 , H01L21/225 , H01L21/285
CPC分类号： H01L29/66575 , H01L21/2257 , H01L29/41783 , H01L29/665 , H01L29/66545
摘要： A method for forming a ultra-shallow junction region (104). A silicon film (single crystalline, polycrystalline or amorphous) is deposited on the substrate (100) to form an elevated S/D (106). A metal film is deposited over the silicon film and reacted with the silicon film to form a silicide film (108). The silicon film is preferably completely consumed by the silicide film formation. An implant is performed to implant the desired dopant either into the metal film prior to silicide formation or into the silicide film after silicide formation. A high temperature anneal is used to drive the dopant out of the silicide film to form the junction regions (104) having a depth in the substrate (100) less than 200A. This high temperature anneal may be one of the anneals that are part of the silicide process or it may be an additional process step.
摘要翻译：一种形成超浅结区域（104）的方法。在衬底（100）上沉积硅膜（单晶，多晶或无定形）以形成升高的S / D（106）。在硅膜上沉积金属膜并与硅膜反应形成硅化物膜（108）。硅膜优选被硅化物膜形成完全消耗。进行植入以在硅化物形成之前将期望的掺杂剂注入到金属膜中，或者在硅化物形成之后进入硅化物膜。使用高温退火来将掺杂剂驱出硅化物膜以形成在衬底（100）中具有小于200A的深度的结区（104）。该高温退火可以是作为硅化物工艺的一部分的退火之一，或者可以是额外的工艺步骤。

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