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61. 发明授权

EP0436077B1 Multiplexed serial register architecture for VRAM 失效
标题翻译： VRAM的串行复用寄存器架构
公开(公告)号：EP0436077B1
公开(公告)日：1996-09-04
申请号：EP90119442.3
申请日：1990-10-10
申请人： International Business Machines Corporation
发明人： Hiltebeitel, Nathan Rafael , Tamlyn, Robert , Tomashot, Steven William
IPC分类号： G11C11/409
CPC分类号： G11C11/4096

62. 发明公开

EP0646928A3 Synchronous dynamic random access memory 失效
标题翻译：同步电动机Dichtzugriffspeicher。
公开(公告)号：EP0646928A3
公开(公告)日：1996-04-24
申请号：EP94115367.8
申请日：1994-09-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Toda, Haruki
IPC分类号： G11C11/409
CPC分类号： G11C7/10 , G11C7/103 , G11C7/1072 , G11C11/4096
摘要： A synchronous DRAM has cell arrays arranged in matrix, divided into banks accessed asynchronously, and n bit I/O buses for transferring data among the cell arrays. In the DRAM, the banks are divided into m blocks, the n-bit I/O buses located between adjacent banks, is used for time sharing between adjacent banks in common, the n bit I/O buses, used for time sharing between adjacent banks in common, are grouped into n/m-bit I/O buses, every n/m bits for each block of m blocks of bank, and in each block in each bank, data input/output are carried out between the n/m-bit I/O buses and data bus lines in each block. A synchronous DRAM includes a first and second internal clock systems for controlling a burst data transfer in which a string of burst data being transferred in synchronism with an external clock signal, when one of the internal clock systems is driven, the burst data transfer is commenced immediately by the selected internal clock system.
摘要翻译：同步DRAM具有排列成矩阵的单元阵列，被划分为异步访问的单元，以及用于在单元阵列之间传送数据的n位I / O总线。在DRAM中，银行分为m个块，位于相邻bank之间的n位I / O总线用于相邻bank之间的时间共享，n位I / O总线用于在相邻bank之间进行时间共享共同组合被分组为n / m位I / O总线，每个m个块的每个块的每n / m位，并且在每个存储体的每个块中，数据输入/输出在n / 每个块中的m位I / O总线和数据总线。同步DRAM包括用于控制突发数据传输的第一和第二内部时钟系统，其中当内部时钟系统中的一个被驱动时，突发数据传输开始，其中一串突发数据正在与外部时钟信号同步传输立即由选定的内部时钟系统。

63. 发明公开

EP0680049A3 Synchronizer 失效
标题翻译：同步。
公开(公告)号：EP0680049A3
公开(公告)日：1996-01-17
申请号：EP94309206.4
申请日：1994-12-09
申请人： Mosaid Technologies Incorporated
发明人： Millar, Bruce , Foss, Richard C. , Wojcicki, Tomasz
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/1093 , G11C7/1078 , G11C11/4096
摘要： A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) comprised of a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch.

64. 发明公开

EP0673036A2 Semiconductor memory device having split transfer function 失效
标题翻译： Halbleiterspeicheranordnung mit geteiltemÜbertragungsbetrieb。
公开(公告)号：EP0673036A2
公开(公告)日：1995-09-20
申请号：EP95103850.4
申请日：1995-03-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagasaka, Shigeki
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/1075
摘要： A semiconductor memory device including a serial I/O buffer (19); DRAM cells (1); and SAM cells (4,5) arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells (4,5) are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer (19) sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells (4,5) are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer (19) sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer. The semiconductor memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating a first and a second signals. When a mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.
摘要翻译：一种包括串行I / O缓冲器（19）的半导体存储器件; DRAM单元（1）; 和SAM单元（4,5），SAM单元对应于一行中的DRAM单元。在第一模式的装置中，SAM单元（4,5）被划分为每个具有边界的N个第一部分，存储在SAM单元中的数据被依次传送到串行I / O缓冲器（19），直到SAM单元第一部分的边界被传送到串行I / O缓冲器。在第二模式中，SAM单元（4,5）被分成具有边界的M（N> M）个第二部分，存储在SAM单元中的数据被依次传送到串行I / O缓冲器（19），直到SAM 第二部分边界的单元被传送到串行输入输出缓冲器。半导体存储器件还包括用于检测从第一模式到第二模式以及从第二模式到第一模式的变化的电路。半导体存储器件还包括用于产生第一和第二信号的电路。当模式从第一模式改变到第二模式时，电路产生第一信号。当模式从第二模式改变到第一模式时，电路产生第二信号。

65. 发明公开

EP0525068A4 INTEGRATED CIRCUIT I/O USING A HIGH PREFORMANCE BUS INTERFACE 无效
标题翻译：集成电路I / O使用高预置总线接口
公开(公告)号：EP0525068A4
公开(公告)日：1995-09-20
申请号：EP91908374
申请日：1991-04-16
申请人： RAMBUS INC
发明人： FARMWALD MICHAEL , HOROWITZ MARK
IPC分类号： G06F1/10 , G06F11/00 , G06F11/10 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/16 , G06F13/376 , G11C5/00 , G11C5/06 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C29/00
CPC分类号： G11C7/1066 , G06F11/006 , G06F11/1048 , G06F12/0215 , G06F12/0661 , G06F12/0684 , G06F13/1605 , G06F13/161 , G06F13/1678 , G06F13/1689 , G06F13/1694 , G06F13/376 , G06F13/4239 , G11C5/00 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/066 , G11C7/1006 , G11C7/1012 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/00 , G11C11/4076 , G11C11/4096 , G11C29/88 , G11C2207/105 , G11C2207/108 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

66. 发明授权

EP0398510B1 Video random access memory 失效
标题翻译：视频Direktzugriffsspeicher。
公开(公告)号：EP0398510B1
公开(公告)日：1995-02-08
申请号：EP90304325.5
申请日：1990-04-23
申请人： International Business Machines Corporation
发明人： Gupta, Satish , Henderson, Randall Lawrence , Hiltebeitel, Nathan Rafael , Tamlyn, Robert , Tomashot, Steven William , Williams, Todd
IPC分类号： G11C8/00 , G11C7/00 , G11C11/409
CPC分类号： G11C11/4096 , G11C7/1075 , G11C8/00

67. 发明公开

EP0534394A3 Semiconductor memory device and method for controlling its output 失效
标题翻译：半导体存储器件和用于控制其输出的方法
公开(公告)号：EP0534394A3
公开(公告)日：1994-12-28
申请号：EP92116261.6
申请日：1992-09-23
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Nagase, Koichi, c/o Mitsubishi Denki , Nakayama, Akio, c/o Mitsubishi Denki , Aono, Tetsuya, c/o Mitsubishi Denki , Ikeda, Yutaka, c/o Mitsubishi Denki , Mizugai, Yoshinori, c/o Mitsubishi Denki
IPC分类号： G11C11/24 , G06F13/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C8/18 , G11C11/4096 , G11C2207/108
摘要： An upper column address strobe signal CAS U ¯ and a lower column address strobe signal CAS L ¯ applied to a dynamic RAM 100 are 180° out of phase from each other. Data of n bits are read out from a memory cell array 105 at a time. The data read out from memory cell array 105 is divided into two bit groups and applied to an upper IO buffer 107 and a lower IO buffer 108. Upper IO buffer 107 and lower IO buffer 108 latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus 2 in response to the upper column address strobe signal CAS U ¯ and the lower column address strobe signal CAS L ¯ .
摘要翻译：施加到动态RAM 100的较高列地址选通信号CASU-和较低列地址选通信号CASL-彼此相差180°。 n位的数据一次从存储单元阵列105中读出。从存储器单元阵列105读出的数据被分成两个比特组并且被施加到上IO缓冲器107和下IO缓冲器108.上IO缓冲器107和下IO缓冲器108顺序地锁存高位比特组和低位比特组并响应于较高列地址选通信号CASU-和较低列地址选通信号CASL-将这些组输出到数据传输总线2。

68. 发明公开

EP0618585A3 Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines 失效
标题翻译：与用于通过少量的数据线输出的数据位的一个外部时钟信号同步半导体存储器件。
公开(公告)号：EP0618585A3
公开(公告)日：1994-12-14
申请号：EP94105060.1
申请日：1994-03-30
申请人： NEC CORPORATION
发明人： Takai, Yasuhiro, c/o NEC Corporation
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C11/4096 , G11C7/1039 , G11C7/1072
摘要： A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal (CK), and a column addressing system (151) incorporated in the synchronous dynamic random access memory device forms a plurality of pipeline stages (150c/150d; 150e; DFF4/DFF5) together with an input/ output unit (161) for sequentially supplying data bits to a data port (DP10) in response to a column address (DC1) internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus (161a).

69. 发明公开

EP0618585A2 Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines 失效
标题翻译：与用于通过少量的数据线输出的数据位的一个外部时钟信号同步半导体存储器件。
公开(公告)号：EP0618585A2
公开(公告)日：1994-10-05
申请号：EP94105060.1
申请日：1994-03-30
申请人： NEC CORPORATION
发明人： Takai, Yasuhiro, c/o NEC Corporation
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C11/4096 , G11C7/1039 , G11C7/1072
摘要： A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal (CK), and a column addressing system (151) incorporated in the synchronous dynamic random access memory device forms a plurality of pipeline stages (150c/150d; 150e; DFF4/DFF5) together with an input/ output unit (161) for sequentially supplying data bits to a data port (DP10) in response to a column address (DC1) internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus (161a).
摘要翻译：同步动态随机存取存储器设备允许外部设备在同步与系统时钟信号（CK）顺序地访问读出的数据位，并且在同步动态随机存取存储器设备中包含一个列寻址系统（151）形成多个与在输入一起/输出单元（161），用于顺序地响应于一个列地址（DC1）同步内部递增与提供数据比特的数据端口（DP10）;流水线阶段（DFF4 / DFF5 150C / 150D，150E）的系统时钟信号，从而通过单个数据总线（161A）中传播的数据位。

70. 发明公开

EP0591752A3 Multiport memory 失效
标题翻译：多媒体内存
公开(公告)号：EP0591752A3
公开(公告)日：1994-09-14
申请号：EP93115176.5
申请日：1993-09-21
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Matsumoto, Naoki, c/o Intellectual Property Div. , Ikawa, Tatsuo, c/o Intellectual Property Div. , Oshima, Shigeo, c/o Intellectual Property Div.
IPC分类号： G11C11/409 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/1075
摘要： A multiport memory comprises a pair of memory cells (21), at least a pair of bit line (BL, BL ¯ ) and a pair of word lines (WL, WL) on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines (DQ, DQ ¯ ) which are respectively connected to load elements (26, 27) are also provided in the random access port side of the multiport memory. A first switch circuit (24, 25) is connected between the pair of bit lines (BL, BL ¯ ) and the pair of data lines (DQ, DQ ¯ ). On a serial access port side, a data register (30) is connected between the pair of bit lines (BL, BL ¯ ) to receive data transmitted through the pair of bit lines. A second switch circuit (28, 29) for transmitting data is connected between the pair of bit lines (BL, BL ¯ ) and the data register (30). A control circuit (11, 12) opens the first switch circuit (24, 25), before closing the second switch circuit (28, 29) to transmit data stored in the memory cells to the data register.

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