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1. 发明公开

EP0673036A2 Semiconductor memory device having split transfer function 失效
标题翻译： Halbleiterspeicheranordnung mit geteiltemÜbertragungsbetrieb。
公开(公告)号：EP0673036A2
公开(公告)日：1995-09-20
申请号：EP95103850.4
申请日：1995-03-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagasaka, Shigeki
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/1075
摘要： A semiconductor memory device including a serial I/O buffer (19); DRAM cells (1); and SAM cells (4,5) arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells (4,5) are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer (19) sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells (4,5) are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer (19) sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer. The semiconductor memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating a first and a second signals. When a mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.
摘要翻译：一种包括串行I / O缓冲器（19）的半导体存储器件; DRAM单元（1）; 和SAM单元（4,5），SAM单元对应于一行中的DRAM单元。在第一模式的装置中，SAM单元（4,5）被划分为每个具有边界的N个第一部分，存储在SAM单元中的数据被依次传送到串行I / O缓冲器（19），直到SAM单元第一部分的边界被传送到串行I / O缓冲器。在第二模式中，SAM单元（4,5）被分成具有边界的M（N> M）个第二部分，存储在SAM单元中的数据被依次传送到串行I / O缓冲器（19），直到SAM 第二部分边界的单元被传送到串行输入输出缓冲器。半导体存储器件还包括用于检测从第一模式到第二模式以及从第二模式到第一模式的变化的电路。半导体存储器件还包括用于产生第一和第二信号的电路。当模式从第一模式改变到第二模式时，电路产生第一信号。当模式从第二模式改变到第一模式时，电路产生第二信号。

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