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61. 发明公开

EP1248266A2 Control circuit and semiconductor memory device 有权
标题翻译： Steuerungsschaltung und Halbleiterspeicheranordnung
公开(公告)号：EP1248266A2
公开(公告)日：2002-10-09
申请号：EP02250105.0
申请日：2002-01-08
申请人： FUJITSU LIMITED
发明人： Ito, Shigemasa, c/o Fujitsu VLSI Limited
IPC分类号： G11C11/406 , G11C11/4076
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615 , G11C11/4076
摘要： A control circuit is disclosed for increasing the speed of a device responding to a control request from an external device when the external control request is overlapped with an internal control request. The control circuit includes a first signal processing unit (31) for receiving the first control signal and generating a first processed signal. The first signal processing unit includes a filter (35) for filtering the first control signal. A second signal processing unit (32) receives the first control signal and generates a second processed signal. An arbiter (33) receives the second processed signal and the second control signal, determines which one of the received signals is to be given priority, and generates a determination signal based on the determination. A main signal generator (34) generates the main signal from the determination signal or the first processed signal based on the determination signal.
摘要翻译：公开了一种控制电路，用于当外部控制请求与内部控制请求重叠时，提高响应于来自外部设备的控制请求的设备的速度。控制电路包括用于接收第一控制信号并产生第一处理信号的第一信号处理单元（31）。第一信号处理单元包括用于对第一控制信号进行滤波的滤波器（35）。第二信号处理单元（32）接收第一控制信号并产生第二处理信号。仲裁器（33）接收第二处理信号和第二控制信号，确定接收信号中的哪一个被给予优先级，并且基于该确定产生确定信号。主信号发生器（34）基于确定信号从确定信号或第一处理信号产生主信号。

62. 发明公开

EP1050882A2 Methods for operating semiconductor memory devices and semiconductor memory devices 有权
标题翻译： Halbleiterspeicheranordnungen und ihre Betriebsverfahren
公开(公告)号：EP1050882A2
公开(公告)日：2000-11-08
申请号：EP00303775.1
申请日：2000-05-05
申请人： FUJITSU LIMITED
发明人： Suzuki, Takaaki, c/o Fujitsu Limited , Uchida, Toshiya, c/o Fujitsu Limited , Sato, Kotoku, c/o Fujitsu Limited , Yagishita, Yoshimasa, c/o Fujitsu Limited
IPC分类号： G11C5/06
CPC分类号： G11C11/406 , G11C5/066 , G11C11/40603 , G11C11/40611
摘要： A semiconductor memory device having a plurality of operating modes for controlling an internal circuit comprises a command controlling circuit which accepts signals supplied to predetermined terminals as commands at a plurality of times. The number of operating modes is sequentially narrowed down based on each command and the internal circuit is controlled according to the narrowed operating modes. One such command controlling circuit comprises a plurality of accepting circuits (94a). Each of the accepting circuits (94a) respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit (94a) is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.
Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.
摘要翻译：具有用于控制内部电路的多个操作模式的半导体存储器件包括命令控制电路，其接受作为命令多次提供给预定端子的信号。基于每个命令，操作模式的数量依次变窄，并且根据变窄的操作模式来控制内部电路。一个这样的指令控制电路包括多个接受电路（94a）。每个接受电路（94a）分别接收每次多次提供的信号。换句话说，根据信号补充的定时，分别操作不同的接受电路（94a），并且控制内部电路。因此，即使在具有复杂的指令组合的半导体存储器件中，命令控制电路也可以容易地设计。因此，它能够方便验证设计。由于多次接受确定操作模式所需的信息，因此可以减少输入命令所需的终端数量。特别地，在专用端子输入命令的情况下，不再需要其输入焊盘，输入电路等，从而可以减小芯片尺寸。通过减少端子数量来实现减少，这限制了封装尺寸。

63. 发明公开

EP4379561A1 MEMORY SYSTEM AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：EP4379561A1
公开(公告)日：2024-06-05
申请号：EP23205865.1
申请日：2023-10-25
申请人： Samsung Electronics Co., Ltd.
发明人： CHOI, Kyungeun , CHEONG, Wooseong
IPC分类号： G06F13/16 , G11C11/406
CPC分类号： G06F13/1636 , G11C11/40603 , G11C11/40618
摘要： Provided are a memory system and an operating method of the memory system. The memory system includes a memory controller configured to generate a first command and a second command in response to receiving a sequential command from a host, and a first memory device and a second memory device each configured to receive the first command and the second command, wherein the sequential command is a command to determine or indicate whether to access each of the first memory device and the second memory device, and the memory controller is further configured to determine whether to access at least one memory device among the first and second memory devices, transmit the first command to the first memory device when the first memory device is to be accessed, and transmit the second command to the second memory device when the second memory device is not to be accessed.

64. 发明公开

EP3055863A1 DATA PROCESSOR WITH MEMORY CONTROLLER FOR HIGH RELIABILITY OPERATION AND METHOD 有权转让
标题翻译：带记忆控制与可靠性和程序使用数据处理器
公开(公告)号：EP3055863A1
公开(公告)日：2016-08-17
申请号：EP14852387.1
申请日：2014-10-06
申请人： Advanced Micro Devices, Inc.
发明人： BRANDL, Kevin M.
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G06F13/1605 , G06F13/1642
摘要： A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (t
RCPAGE ) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.
摘要翻译：一种数据处理器，包括存储器访问剂和存储器控制器。该存储器存取代理基因费率的访问的存储器中的多个。所述存储器控制器被耦合到所述存储器存取代理和时间表的存储器中的多个基于存储器的特性的顺序访问。存储器的特征包括一个行周期时间页（tRCPAGE）指示激活命令的预定时间窗口内的可接受的编号，以在所述存储器中的行的。

65. 发明公开

EP2600253A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 有权转让
标题翻译： HALBLEITERVORRICHTUNG UND DATENVERARBEITUNGSSYSTEM
公开(公告)号：EP2600253A1
公开(公告)日：2013-06-05
申请号：EP11812196.1
申请日：2011-06-21
申请人： Renesas Electronics Corporation
发明人： SATO, Junkei , HONDA, Nobuhiko
IPC分类号： G06F12/00 , G11C11/401 , G11C11/407
CPC分类号： G11C7/1072 , G06F13/1636 , G06F13/1689 , G06F13/4234 , G11C7/1057 , G11C7/1084 , G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession.
The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.
摘要翻译：提供了一种用于避免刷新命令的问题和校准命令的问题被连续排列的存储器控制技术。存储器控制电路基于设置的刷新周期发出刷新命令以进行刷新操作，并且基于设定的校准周期发出校准命令以进行校准操作的请求，对于该校准周期，抑制仅在发出刷新命令之后的给定时间发出校准命令，并且仅在发出校准命令之后的给定时间内抑制刷新命令的问题。

66. 发明授权

EP1657723B1 SEMICONDUCTOR MEMORY AND OPERATION METHOD OF SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器用于操作半导体存储器
公开(公告)号：EP1657723B1
公开(公告)日：2013-03-06
申请号：EP03818115.2
申请日：2003-08-18
申请人： Fujitsu Semiconductor Limited
发明人： ETO, Satoshi, c/o FUJITSU LIMITED
IPC分类号： G11C29/52 , G11C11/4076 , G11C11/406 , G11C7/10 , G06F11/10
CPC分类号： G11C11/4076 , G11C7/1006 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C29/52 , G11C2207/104 , G11C2211/4061 , G11C2211/4062 , G11C2211/4067

67. 发明公开

EP2372558A3 Dynamic memory supporting simultaneous refresh and data-access transactions 审中-公开
标题翻译：与支持的同时刷新和数据存取交易动态内存
公开(公告)号：EP2372558A3
公开(公告)日：2011-10-19
申请号：EP11171486.1
申请日：2003-10-09
申请人： Rambus Inc.
发明人： Ware, Frederick, A. , Perego, Richard, E.
IPC分类号： G06F12/00 , G11C11/406 , G06F13/16
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

68. 发明公开

EP2372559A2 Dynamic memory supporting simultaneous refresh and data-access transactions 审中-公开
标题翻译：支持同时刷新和数据访问事务的动态内存
公开(公告)号：EP2372559A2
公开(公告)日：2011-10-05
申请号：EP11171622.1
申请日：2003-10-09
申请人： Rambus Inc.
发明人： Ware, Frederick, A. , Perego, Richard, E.
IPC分类号： G06F12/00 , G11C11/406 , G06F13/16
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.
摘要翻译：所描述的是执行重叠刷新和数据访问（读取或写入）交易的动态存储器系统，其将刷新事务对存储器性能的影响最小化。存储器系统支持针对不同银行的独立且同时激活和预充电操作。两组地址寄存器使系统能够同时指定不同的存储区进行刷新和数据访问事务。

69. 发明公开

EP2284838A1 Semiconductor memory, memory controller, system, and operating method of semiconductor memory 有权
标题翻译： Halbleiterspeicher，Speichersteuerung，System und Betriebsverfahrenfüreinen Halbleiterspeicher
公开(公告)号：EP2284838A1
公开(公告)日：2011-02-16
申请号：EP10182639.4
申请日：2008-02-27
申请人： Fujitsu Semiconductor Limited
发明人： Kawabata, Kuninori
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A memory controller controlling operations of a plurality of semiconductor memories each having dynamic memory cells, in response to an access request from a system controller and a refresh request, the memory controller comprising: a refresh request generation circuit (14) periodically outputting the refresh request; a main refresh address counter (MRAC) changing a main block address held in the main refresh address counter, when the main block address coincides with an access block address corresponding to the access request, and sequentially generating a main row address and the main block address in synchronization with a main count signal; a sub refresh address counter (SRAC) set valid when the main block address coincides with the access block address, receiving, as a sub block address and a sub row address, the main block address and the main row address transferred from the main refresh address counter, sequentially generating the sub row address in synchronization with a sub count signal, and set invalid after outputting a final sub row address; an address selection circuit (RASEL, BASEL) selecting addresses not coinciding with the access block address, out of the main block address and the main row address, and the sub block address and the sub row address, and outputting the selected addresses; a counter control circuit (CCNT) outputting, in response to a refresh request, one of the main count signal and the sub count signal corresponding to the addresses output by the address selection circuit; a refresh counter control circuit (MCMP, SW1, F/F, AND1, SW2, SCMP, AND2) controlling operations of the main refresh address counter, the sub refresh address counter, the address selection circuit, and the counter control circuit, and making the sub refresh address counter operate with priority over the main refresh address counter during a period in which the sub refresh address counter is valid; and an operation control circuit (16) outputting an access control signal in response to the access request, and outputting a refresh control signal in response to the refresh.
摘要翻译：存储器控制器，响应于来自系统控制器的访问请求和刷新请求，控制各自具有动态存储单元的多个半导体存储器的操作，所述存储器控制器包括：周期性地输出刷新请求的刷新请求生成电路（14） ; 当主块地址与对应于访问请求的访问块地址一致时，主要刷新地址计数器（MRAC）改变保存在主刷新地址计数器中的主块地址，并且顺序地产生主行地址和主块地址与主计数信号同步; 当主块地址与访问块地址一致时，子刷新地址计数器（SRAC）设置为有效，接收从主刷新地址传送的主块地址和主行地址作为子块地址和子行地址计数器，与子计数信号同步顺序地产生子行地址，并在输出最后的子行地址后设置为无效; 选择地址选择电路（RASEL，BASEL），从主块地址和主行地址以及子块地址和子行地址中选择与访问块地址不一致的地址，并输出所选择的地址; 响应于刷新请求，计数器控制电路（CCNT）输出与地址选择电路输出的地址对应的主计数信号和副计数信号之一; 控制主刷新地址计数器，副刷新地址计数器，地址选择电路和计数器控制电路的操作的刷新计数器控制电路（MCMP，SW1，F / F，AND1，SW2，SCMP，AND2）子刷新地址计数器在副刷新地址计数器有效的时间段内优先地操作主刷新地址计数器; 以及响应于所述访问请求输出访问控制信号的操作控制电路（16），并且响应于所述刷新而输出刷新控制信号。

70. 发明授权

EP1746606B1 Memory circuit having parity cell array 有权
标题翻译：具有奇偶校验单元阵列存储器电路
公开(公告)号：EP1746606B1
公开(公告)日：2010-03-31
申请号：EP06021810.4
申请日：2002-10-22
申请人： Fujitsu Microelectronics Limited
发明人： Fujioka, Shinya , Fujieda, Waichiro , Hara, Kota , Koga, Toru , Mori, Katsuhiro
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/106 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C2211/4062

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