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61. 发明授权

EP0082682B1 Microcomputer unit 失效
标题翻译：微型计算机单元
公开(公告)号：EP0082682B1
公开(公告)日：1989-10-11
申请号：EP82306728.5
申请日：1982-12-16
申请人： FUJITSU LIMITED
发明人： Suzuki, Tetsuo , Nishikawa, Senji
IPC分类号： G06F11/00 , G06F11/30
CPC分类号： G06F11/3656 , G06F11/22

62. 发明公开

EP0333593A2 A data processing system capable of fault diagnosis 失效
标题翻译：诊断系统在einem Datenverarbeitungssystem。
公开(公告)号：EP0333593A2
公开(公告)日：1989-09-20
申请号：EP89400745.9
申请日：1989-03-16
申请人： FUJITSU LIMITED
发明人： Kawamoto, Masakazu
IPC分类号： G06F11/22
CPC分类号： G06F11/2736 , G06F11/22
摘要： A diagnostic system in a data processing system constituted by management module (1a) and a plurality of function modules (2a,...,2n) connected to the management module through a common bus line (3), the diagnostic system including: a service line (4) connected to the management module and the plurality of function modules for issuing a diagnostic mode command; a diagnostic line (30) connected to the management module (1a) and the plurality of function modules for indicating a transfer of diagnostic data on the common bus line; a diagnostic mode storage unit (200) provided in each of the function modules, and operatively connected to the service line for setting the diagnostic mode; and a comparison unit (201) provided in each of the function modules, and operatively connected to the diagnostic mode storage unit (200) and the diagnostic line (30).
摘要翻译：一种由管理模块（1a）和通过公共总线（3）连接到管理模块的多个功能模块（2a，...，2n）构成的数据处理系统中的诊断系统，所述诊断系统包括：连接到管理模块的服务线（4）和用于发出诊断模式命令的多个功能模块; 连接到管理模块（1a）的诊断线（30）和用于指示在公共总线上传送诊断数据的多个功能模块; 诊断模式存储单元（200），设置在每个功能模块中，并且可操作地连接到所述服务线以设置所述诊断模式; 以及设置在每个功能模块中并且可操作地连接到诊断模式存储单元（200）和诊断线（30）的比较单元（201）。

63. 发明公开

EP0325079A1 Device for controlling the channel adapters in a data processing system remotely 失效
标题翻译：在einem Datenverarbeitungssystem中的Vorrichtung zur Fernsteuerung der Kanaladapter。
公开(公告)号：EP0325079A1
公开(公告)日：1989-07-26
申请号：EP88480003.8
申请日：1988-01-22
申请人： International Business Machines Corporation
发明人： Pierre, Anne , Vachee, Pierre , Robbe, Jean-Claude , Leroy, Serge
IPC分类号： G06F15/16 , G06F11/22
CPC分类号： G06F15/177 , G06F11/22
摘要： The data handling system which incorporates the channel adpater control mechanism comprises a central control unit (30) attached to at least one host system through channel adapters (40) and a service processor (44) comprising a microprocessor running a program, attached to the central control unit and to at least one operator console through an input/output bus (104).
The mechanism comprises a service processor interfacing means (78) attached to the input/output bus (104) and comprising register means into which the microprocessor causes bit configurations to be written in response to commands issued from one operator console or from the microprocessor program, said bit configurations being indicative of a desired status of the channel adapters,
control means (80,112) for providing the bit configurations read from the register means to the channel adapter(s), whereby each of them may be set into the desired status, as indicated by the bit configurations.
摘要翻译：结合频道接收机控制机制的数据处理系统包括通过通道适配器（40）连接到至少一个主机系统的中央控制单元（30）和包括运行程序的微处理器（44），服务处理器控制单元以及至少一个操作员控制台通过输入/输出总线（104）。该机构包括附接到输入/输出总线（104）的服务处理器接口装置（78），并且包括寄存器装置，微处理器响应于从一个操作员控制台或微处理器程序发出的命令来写入位配置，所述位配置指示通道适配器的期望状态，用于将从寄存器装置读取的位配置提供给通道适配器的控制装置（80,112），由此可以将它们中的每一个设置为期望状态，如由位配置指示。

64. 发明公开

EP0282628A3 Dual path bus structure for computer interconnection 失效
标题翻译：计算机互连的双路总线结构
公开(公告)号：EP0282628A3
公开(公告)日：1989-01-25
申请号：EP87112180.2
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F13/36
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

65. 发明授权

EP0094179B1 Computer interconnection part 失效
标题翻译：计算机互连部分
公开(公告)号：EP0094179B1
公开(公告)日：1988-11-09
申请号：EP83302413.6
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F11/22 , G06F11/20 , G06F13/36 , G06F13/40
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022

66. 发明公开

EP0282628A2 Dual path bus structure for computer interconnection 失效
标题翻译： Zweifachbusstrukturfürdie Rechnerverbindung。
公开(公告)号：EP0282628A2
公开(公告)日：1988-09-21
申请号：EP87112180.2
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F13/36
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly.
Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput.
Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
摘要翻译：一种用于需要高可用性和通信可靠性的计算机网络中的总线结构。提供多个总线路径（2A，2B）。当要进行传输时，在大多数情况下，随机选择路径，所有路径都是同等可能的。因此，快速检测路径的故障。网络中的每个主机设备通过接口或端口（1）连接到总线路径。路由选择的任务由端口执行，独立于主机设备。这些端口还检测到路径故障，并且在检测到这样的故障时自动切换到备用的良好路径，所有这些都没有主机参与。主机之间的虚拟电路通信对于路径选择和切换是透明的，因此对主机设备进行路径故障的唯一指示是吞吐量的降低。每个端口（10,20A，20B）的信号处理设备的大部分由路径共享，在任何给定时间仅支持一条路径。因此，添加第二总线路径只需要最小的成本。

67. 发明授权

EP0074704B1 Subsystem controller 有权转让
标题翻译：子系统控制器
公开(公告)号：EP0074704B1
公开(公告)日：1988-02-03
申请号：EP82303448.3
申请日：1982-07-01
申请人： UNISYS CORPORATION
发明人： Catiller, Robert Douglas , Harris, Craig Weaver , Mathews, Ronald Dean
IPC分类号： G06F13/12 , G06F15/16
CPC分类号： G06F13/385 , G06F11/22

68. 发明公开

EP0247605A2 System management apparatus for a multiprocessor system 失效转让
标题翻译： Systemverwaltungsgerätfürein Mehrprozessorsystem。
公开(公告)号：EP0247605A2
公开(公告)日：1987-12-02
申请号：EP87107746.7
申请日：1987-05-27
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Carroll, Elmer W. , Keeley, James W. , Martland, Wallace A. , Morganti, Victor M. , Peters, Arthur , Zelley, Richard C.
IPC分类号： G06F11/30
CPC分类号： G06F11/328 , G06F11/0724 , G06F11/0757 , G06F11/22 , G06F11/2294 , G06F11/32 , G06F11/321
摘要： A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.
摘要翻译：数据处理单元包括多个紧密耦合的中央子系统，多个外围子系统，主存储器和系统管理设备，其全部共同连接到系统总线。系统管理单元在系统总线上具有最高优先级，并且包括提供用于指示功率和温度状态，启动子系统，测试子系统，定时中心子系统功能以及允许本地和远程维护对子系统的访问的设备的集中式资源。系统管理设施从中央子系统接收命令，读取和写入定时器，以及读取整个系统的状态。系统管理设备为中央子系统生成特殊命令，以指示定时器什么时候减少到零，以及特殊命令来辅助硬件和软件调试。

69. 发明公开

EP0190370A1 Device for improving the detection of non-operational states in a non-attended interrupt-driven processor 有权
标题翻译：装置用于在非操作中断驱动的处理器检测出服务状态中的。
公开(公告)号：EP0190370A1
公开(公告)日：1986-08-13
申请号：EP84430050.9
申请日：1984-12-31
申请人： International Business Machines Corporation , Compagnie IBM FRANCE
发明人： Combes, Jacques , Robbe, Jean-Claude , Viallon, Paul
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/22 , G06F11/0757
摘要： Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching an unoperational state detection task running on the n-1 priority level at time intervals smallerthan a specified time-out delay. A detection timer (1) which is set at an initial value each time the task is dispatched and the content of which is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and which are reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.

70. 发明公开

EP0184657A2 Multicomputer digital processing system 失效
标题翻译：数字多计算机处理系统。
公开(公告)号：EP0184657A2
公开(公告)日：1986-06-18
申请号：EP85113839.6
申请日：1985-10-30
申请人： Flexible Computer Corporation
发明人： Matelan, M. Nicholas , Leete, Thomas G. , Zsohar, Leslie , Blanchard, Michael Kent , Naeini, Abdolreza , Hsu, Jacob , Smith, Dennis Kyle
IPC分类号： G06F9/46 , G06F13/36 , G06F13/40
CPC分类号： G06F11/2023 , G06F1/10 , G06F9/52 , G06F11/2043 , G06F11/22 , G06F11/2736 , G06F11/3466 , G06F13/36 , G06F13/4027 , H01R12/7088 , H05K7/1459
摘要： @ A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability unter operator supervision.

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