专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2718818B1 PROCESSING OPERATOR MESSAGE COMMANDS 有权
公开(公告)号：EP2718818B1
公开(公告)日：2018-10-03
申请号：EP12796562.2
申请日：2012-06-06
申请人： International Business Machines Corporation
发明人： SHAW, Thomas , GOSS, Steven, Neil , ELKO, David
IPC分类号： G06F11/22
CPC分类号： G06F9/544 , G06F9/5077 , G06F9/54 , G06F11/22
摘要： A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.

2. 发明公开

EP3321807A4 DISK DETECTION METHOD AND DEVICE 有权
公开(公告)号：EP3321807A4
公开(公告)日：2018-06-20
申请号：EP16832103
申请日：2016-04-27
申请人： HUAWEI TECH CO LTD
发明人： LI JINGHUI , ZHANG JINDONG , HUANG CHENG
IPC分类号： G06F11/22 , G06F11/30 , G06F11/34
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0689 , G06F11/22 , G06F11/3034 , G06F11/3419 , G06F11/3485
摘要： The present invention provides a disk detection method and apparatus. The method includes: collecting a set of N pieces of real-time data that are in a one-to-one correspondence with N input/output I/O-related counters of a disk, where the N I/O-related counters include an I/O response time of the disk and a counter affecting the I/O response time; the I/O response time is a time between delivery of an operation request by an application and reception of a response of the disk to the request; and N is an integer greater than or equal to 2; determining, according to the N pieces of real-time data, whether the I/O response time is abnormal, where the I/O response time being abnormal indicates that the disk is incapable of normally running a service, and the I/O response time being normal indicates that the disk is capable of normally running a service; and outputting a detection result if the I/O response time is abnormal, where the detection result is used to represent that the I/O response time is abnormal.

3. 发明公开

EP3040730A3 APPARATUS FOR TESTING SEMICONDUCTOR CHIP HAVING BUILT-IN SELF TEST FUNCTION 审中-公开
标题翻译：设备用于测试半导体芯片内建自测试
公开(公告)号：EP3040730A3
公开(公告)日：2016-08-03
申请号：EP15185743.0
申请日：2015-09-17
申请人： iA, Inc.
发明人： BAE, Jungyang
IPC分类号： G01R31/3187 , G06F11/00 , G01R31/3183
CPC分类号： G01R31/31724 , G01R31/3177 , G01R31/318342 , G01R31/3187 , G06F11/22
摘要： The present invention relates to an apparatus for testing a semiconductor chip in which a built-in self test function is embedded, the apparatus including a plurality of error generators inserted between a plurality of function blocks performing a function of the semiconductor chip to input an error signal into the function blocks; and an external error controller for controlling the error generators through external input and output pins of the semiconductor chip and confirming the built-in self test function of the semiconductor chip by monitoring an output signal of the function blocks, and thus an error detection function embedded in the semiconductor chip can be correctly verified.

4. 发明公开

EP2983156A1 Système et procédé de protection de circuit 无效转让
标题翻译：系统与Verfahren zum Schutz von Schaltkreisen
公开(公告)号：EP2983156A1
公开(公告)日：2016-02-10
申请号：EP14306247.9
申请日：2014-08-06
申请人： Secure-IC SAS
发明人： Guilley, Sylvain , Porteboeuf, Thibault , Danger, Jean-Luc
IPC分类号： G09C1/00 , H04L9/00
CPC分类号： G06F21/75 , G06F11/22 , G06F11/263 , G06F21/55 , G06F21/56 , G06F21/71 , G06F2221/034 , G09C1/00 , H04L9/002 , H04L2209/046 , H04L2209/12
摘要： L'invention propose un procédé de protection d'un circuit booléen associé à une description structurelle du circuit comprenant des variables booléennes élémentaires, chacune représentée par un bit, le procédé comprenant les étapes consistant à:
- sélectionner un ensemble de k variables booléennes élémentaires du circuit en fonction de critères de sélection prédéfinis,
- construire une variable x représentée par k bits par concaténation des k variables sélectionnées, selon un ordre choisi,
- déterminer un code binaire C, comprenant un ensemble de mots de code et appartenant à un espace vectoriel donné, et le code supplémentaire D du code binaire C, en fonction d'une condition portant sur la distance duale du code supplémentaire D, le code binaire C ayant une longueur n et une taille 2 k , où k désigne le nombre de bits représentant la variable x ;
- substituer la variable x dans la description structurelle du circuit booléen par une variable protégée z représentée par n bits de telle sorte que :
- toute opération d'écriture sur la variable x dans le circuit soit substituée par une opération d'écriture sur la variable z, la variable z étant générée par ajout de la variable x encodée par ledit code C à un vecteur de bit d'aléas y encodé par le code supplémentaire D, et
- toute opération de lecture de la variable x dans le circuit soit substituée par une opération de lecture de la valeur de la variable protégée z et d'une opération de décodage de ladite valeur lue de la variable protégée z en utilisant une matrice de décodage J de taille ( n × k ) déterminée à partir du code binaire C et du code supplémentaire D du code binaire C.
摘要翻译：本发明提出了一种保护布尔电路的方法，该布尔电路与包括基本布尔变量的电路的结构描述相关联，每个基本布尔变量由一个位表示，该方法包括以下步骤： - 选择电路的一组k个基本布尔变量作为预定义的选择标准的函数， - 根据所选择的顺序，通过连接k个所选变量来构造由k个比特表示的变量x， - 确定包含一组码字并属于给定向量空间的二进制码C 以及所述二进制码C的补码D作为与所述补码D的双距离有关的条件的函数，所述二进制码C具有长度n和大小2k，其中k表示表示所述补码变量x - 用布尔电路的结构描述中的变量x替换由n位表示的保护变量z，使得： - 对在电路中的变量x进行写入的任何操作都被写入变量z的操作所替代，通过将由所述代码C编码的变量x添加到由补充代码D编码的随机位矢量y来生成变量z，并且 - 读取电路中的变量x的任何操作被读取使用从二进制码C和二进制码C的补充码D确定的大小（nxk）的解码矩阵J来解码受保护变量z的所述读取值的操作。

5. 发明公开

EP2676202A1 GENERATING TEST DATA 审中-公开
标题翻译：创建测试数据的
公开(公告)号：EP2676202A1
公开(公告)日：2013-12-25
申请号：EP11858666.8
申请日：2011-02-18
申请人： Hewlett-Packard Development Company, L.P.
发明人： WEI, Yongdong
IPC分类号： G06F11/36
CPC分类号： G06F11/263 , G03G15/55 , G06F11/0748 , G06F11/22 , G06F11/2294 , G06F11/3672 , G06F11/3684 , G06F17/30943
摘要： A method of generating test data is provided herein. The method includes generating a schema comprising a database table. The method also includes receiving a selection of the database table. Additionally, the method includes receiving one or more rule definitions for populating the database table. The method further includes generating a stored procedure for populating the database table based on the rule definitions and the schema.

6. 发明公开

EP2613212A1 Diagnostic algorithm parameter optimization 有权
标题翻译： Diagnosealgorithmusparameteroptimierung
公开(公告)号：EP2613212A1
公开(公告)日：2013-07-10
申请号：EP13150325.2
申请日：2013-01-04
申请人： Honeywell International Inc.
发明人： Patankar, Raviindra , Iyer, Shreyas , Felke, Tim
IPC分类号： G05B23/02
CPC分类号： G06F17/5022 , G05B23/0243 , G06F11/07 , G06F11/0739 , G06F11/0751 , G06F11/0766 , G06F11/079 , G06F11/22 , G06F11/261 , G06F11/321 , G06F11/366 , G06F17/10 , G06F2207/7271
摘要： A system and method are provided for optimizing parameters of a plurality of selected diagnostic and/or prognostic algorithms in a tunable diagnostic algorithm library. A plurality of sensed data sets having an actual diagnostic label associated therewith is supplied to each of the diagnostic algorithms. A value for each parameter of each of the algorithms that are to be optimized is supplied. A computed diagnostic label is generated for each of the sensed data sets using each of the selected algorithms, a fault model, and the values for each parameter, each of the computed diagnostic labels and each of the actual diagnostic labels are supplied to a generic objective function, to thereby calculate an objective function value, and the value of one or more of the parameters is varied using an optimization routine that repeats certain of these steps until the objective function value is minimized.
摘要翻译：提供了一种用于在可调谐诊断算法库中优化多个选择的诊断和/或预测算法的参数的系统和方法。具有与其相关联的实际诊断标签的多个感测数据组被提供给每个诊断算法。提供要优化的每个算法的每个参数的值。使用每个所选择的算法，故障模型和每个参数的值为每个感测数据集生成计算的诊断标签，将每个计算的诊断标签和每个实际诊断标签提供给通用目标功能，从而计算目标函数值，并且使用重复这些步骤中的某些步骤的优化例程来改变一个或多个参数的值，直到目标函数值最小化。

7. 发明公开

EP2508993A2 Diagnostic self-tests on inflatable personal restraint systems 审中-公开
标题翻译： AufblasbarepersönlicRückhaltesysteme
公开(公告)号：EP2508993A2
公开(公告)日：2012-10-10
申请号：EP12160025.8
申请日：2012-03-19
申请人： AmSafe, Inc.
发明人： Hagan, Willard F. , Smith, Joseph , Shields, Ronald A. , Settles, Peter A.
IPC分类号： G06F11/22 , B60R21/00 , B60W50/00
CPC分类号： G06F11/22 , B64D11/062 , B64D11/06205 , B64D11/0621 , B64D2201/00 , G05B23/0256
摘要： An electronic module assembly (EMA) for use in controlling one or more personal restraint systems. A programmed processor within the EMA is configured to determine when a personal restraint system associated with each seat in a vehicle should be deployed. In addition, the programmed processor is configured to perform a diagnostic self-test to determine if the EMA and the personal restraint systems are operational. In one embodiment, results of the diagnostic self-test routine are displayed on a display included on the electronic module assembly. In an alternative embodiment, the results of the diagnostic self-test routine are transmitted via a wireless transceiver to a remote device. The remote device can include a wireless interrogator or can be a remote computer system such as a cabin management computer system.
摘要翻译：一种用于控制一个或多个个人约束系统的电子模块组件（EMA）。 EMA内的编程处理器被配置为确定何时应该部署与车辆中的每个座椅相关联的个人约束系统。此外，编程处理器被配置为执行诊断自检以确定EMA和个人约束系统是否可操作。在一个实施例中，诊断自检程序的结果被显示在包括在电子模块组件上的显示器上。在替代实施例中，诊断自检程序的结果经由无线收发器发送到远程设备。远程设备可以包括无线询问器，或者可以是诸如客舱管理计算机系统的远程计算机系统。

8. 发明授权

EP0754382B1 A METHOD AND A SYSTEM FOR DISTRIBUTED SUPERVISION OF HARDWARE 失效
标题翻译： VERFAHREN UND系统ZUR VERTEILTEN KONTROLLE VON HARDWARE
公开(公告)号：EP0754382B1
公开(公告)日：2004-11-17
申请号：EP95916075.5
申请日：1995-04-04
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： HABBE, Ingemar , SIMMONDS, Andrew , WAHLMAN, Stefan , GISCOMBE, Ricardo , LENNARTSSON, Magnus , STRÖMME, Per, Einar
IPC分类号： H04L12/26
CPC分类号： H04L43/00 , G06F11/22 , H04L2012/5625 , H04L2012/5627 , H04L2012/5628 , H04Q11/0478
摘要： A fault supervision and management system in a telecommunication system includes a chain system of diagnose and inference objects (IFP) connected after each other in a fault propagation direction in the telecommunication system. The location of these objects in the chain system is determined so as to enable them to supervise, in an own supervision domain, one phenomenon each, which may be caused by faults in the telecommunication system, and to communicate with, affect and interact with each other in case of emergence of a fault, for localizing faults in the telecommunication system. Each diagnose and inference object uses one or more measurement point objects (MEP) for observing the emergence of the phenomenon supervised by the diagnose and inference object, and reporting to the diagnose and inference object (IFP). More measurement point objects (MEP) may be grouped to a measurement combinatory object (MEC) which puts together and processes data from its including measurement point objects.
摘要翻译：在电信系统中，故障监督管理系统包括在故障传播方向上相互连接的诊断和推理对象的链式系统。确定这些对象的位置，使得它们能够在监督领域监督每一种可能由电信系统中的故障引起的现象。这些对象进一步定位，以便在出现故障的情况下使它们能够彼此通信，相互影响和相互作用，以便定位电信系统中的故障。每个诊断和推理对象使用一个或多个测量点对象来观察由诊断和推理对象监督的现象的出现以及用于向诊断和推理对象报告。几个测量点对象可以分组在测量组合对象中，该组合对象将来自测量点对象的数据进行组合和处理。

9. 发明公开

EP0936534A3 Recording device 失效
标题翻译：录音机
公开(公告)号：EP0936534A3
公开(公告)日：2003-08-13
申请号：EP99108417.9
申请日：1992-04-10
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Matsumoto, Toshio, c/o Mitsubishi Denki K.K. , Baba, Hiroshi, c/o Mitsubishi Denki K.K.
IPC分类号： G06F3/06 , G06F11/10 , G06F11/14
CPC分类号： G11C29/74 , G06F11/1076 , G06F11/2015 , G06F11/22 , G06F2211/109
摘要： A recording device which improves a response time to write data by reporting to a host computer (1) the completion of writing operation prior to the completion of writing redundancy data. Data writing command imformation from the host computer is stored in a command/status memory (14) backed up by a power source (16) in an array controller (13), and the completion of writing operation is reported to the host computer at the time of the completion of writing updated data prior to the completion of writing redundancy data. Redundancy data is written as a background process. If redundancy data could not be written due to any abnormality of the power source or the like, such redundancy data may be generated from the data in other disk units of the same redundancy group in accordance with writing command information stored in the command/status memory, thereby completing the writing of redundancy data.

10. 发明授权

EP0916119B1 TRIPLE MODULAR REDUNDANT COMPUTER SYSTEM 失效
标题翻译：三重冗余模块化计算机系统
公开(公告)号：EP0916119B1
公开(公告)日：2001-12-05
申请号：EP97926550.1
申请日：1997-05-15
申请人： Resilience Corporation
发明人： PETIVAN, James, L. , LUNDELL, Donald, C. , LUNDELL, Jonathan, K.
IPC分类号： G06F11/18 , G06F1/04
CPC分类号： G06F11/165 , G06F11/181 , G06F11/182 , G06F11/187 , G06F11/22
摘要： A redundant clock system for use in a computer is provided including a first oscillator which produces first reference clock signals; a second oscillator which produces second reference clock signals; a third oscillator which produces third reference clock signals; a first multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a second multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a third multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a first phase-locked loop (PLL) circuit coupled in a first feedback circuit in which the first PLL receives as reference input the selected reference clock signal provided by the first multiplexer and receives as feedback input a first output clock signal; a second phase-locked loop (PLL) circuit coupled in a second feedback circuit in which the second PLL receives as reference input the selected reference clock signal provided by the second multiplexer and which receives as feedback input the a second output clock signal; a third phase-locked loop (PLL) circuit coupled in a third feedback circuit in which the third PLL receives as reference input the selected reference clock signal provided by the third multiplexer and receives as feedback input a third output clock signal; and a reference clock designation unit which determines whether any one of the first, second or third reference clock signals has failed and which designates one of the two other reference clock signals in the event that one of the reference clock signals has failed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式