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1. 发明授权

EP0479230B1 Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：用于多处理器系统的流水线处理单元回收的方法和装置
公开(公告)号：EP0479230B1
公开(公告)日：1997-06-11
申请号：EP91116756.7
申请日：1991-10-01
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Keeley, James W. , Lemay, Richard A. , Shen, Jian-Kuo , Ledoux, Robert V. , Joyce, Thomas F. , Kelly, Richard P. , Miller, Robert C.
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/004 , G06F11/0724 , G06F11/0766 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the system bus. A unique trap is constructed for signaling the operating system software if the UEV fault was external or internal to the CSS. Also, the contents of all working locations are written into an extended trap save area which enables the operating system to make its own independent decision as to whether the system's integrity has been jeopardized.

2. 发明授权

EP0300166B1 Cache memory having a resiliency in processing a variety of address faults 失效转让
标题翻译：高速缓冲存储器中具有不同地址的故障的处理的弹性。
公开(公告)号：EP0300166B1
公开(公告)日：1995-08-30
申请号：EP88108502.1
申请日：1988-05-27
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Keeley, James W. , Nibby, Chester M., Jr.
IPC分类号： G06F11/00 , G06F12/08
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0757 , G06F11/0793 , G06F11/141 , G06F12/0815

3. 发明公开

EP0479230A3 Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：多处理器系统管道处理单元的恢复方法与装置
公开(公告)号：EP0479230A3
公开(公告)日：1993-03-17
申请号：EP91116756.7
申请日：1991-10-01
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Keeley, James W. , Lemay, Richard A. , Shen, Jian-Kuo , Ledoux, Robert V. , Joyce, Thomas F. , Kelly, Richard P. , Miller, Robert C.
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/004 , G06F11/0724 , G06F11/0766 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the system bus. A unique trap is constructed for signaling the operating system software if the UEV fault was external or internal to the CSS. Also, the contents of all working locations are written into an extended trap save area which enables the operating system to make its own independent decision as to whether the system's integrity has been jeopardized.

4. 发明公开

EP0479230A2 Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译： Wiederherstellungsverfahren undGerätfüreine Pipeline-Verarbeitungseinheit eines Multiprozessor-systems。
公开(公告)号：EP0479230A2
公开(公告)日：1992-04-08
申请号：EP91116756.7
申请日：1991-10-01
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Keeley, James W. , Lemay, Richard A. , Shen, Jian-Kuo , Ledoux, Robert V. , Joyce, Thomas F. , Kelly, Richard P. , Miller, Robert C.
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/004 , G06F11/0724 , G06F11/0766 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the system bus. A unique trap is constructed for signaling the operating system software if the UEV fault was external or internal to the CSS. Also, the contents of all working locations are written into an extended trap save area which enables the operating system to make its own independent decision as to whether the system's integrity has been jeopardized.
摘要翻译：多处理器系统的流水线中央处理系统（CSS）单元被紧密耦合以共同连接到用于共享主存储器和输入/输出控制器/设备的系统总线。除了总线接口单元（BIU）电路之外，CSS还包括用于不同VLSI电路芯片流水线级和相关控制电路的多个电路板。每个电路板包括一个或多个异常事件（UEV）检测器电路，用于在阶段的行为异常时进行信令。来自各板的UEV故障信号由BIU板收集。当检测到UEV故障时，BIU板电路防止与系统总线的任何进一步的通信，并将UEV故障信号广播到其他板，导致不同的流水线阶段模拟管线内的指令的完成，从而冲洗它。之后将其置于非流动模式。控制电路执行UEV处理程序微代码程序，该程序将除了错误信号之外的包含UEV指示符状态的每个板上包括的校验子寄存器的内容读入寄存器文件工作位置。然后清除UEV信号，使得BIU能够恢复与系统总线的通信。如果UEV故障是外部的或内部的，则构建一个唯一的陷阱来发信号通知操作系统软件。此外，所有工作地点的内容都写入扩展的陷阱保存区域，使操作系统能够自行决定系统的完整性是否受到损害。

5. 发明公开

EP0272547A2 Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：一种数据处理系统与由有利于另一个子系统Bussteuerbefehl的一个子系统所产生的信号。
公开(公告)号：EP0272547A2
公开(公告)日：1988-06-29
申请号：EP87118259.8
申请日：1987-12-09
申请人： Bull HN Information Systems Inc.
发明人： Peters, Arthur , Zelley, Richard C. , Carroll, Elmer W. , Barlow, George J. , Nibby, Chester M., Jr. , Keeley, James W.
IPC分类号： G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：一种数据处理系统包括一个系统管理单元，多个中央子系统，一个主存储器和多个外围子系统都共同耦合到一个系统总线。任何子系统可以产生一个命令，其包括：第一字段指定目的地子系统，第二字段指定手术目的地子系统是执行。如果需要一个响应，该子系统产生初始命令可用于接收响应命令指定的第三子系统。

6. 发明公开

EP0258559A2 Cache memory coherency control provided with a read in progress indicating memory 失效转让
标题翻译： Cachespeicherkohärenzsteuerungmit einem Speicher，der ein laufendes Lesen anzeigt。
公开(公告)号：EP0258559A2
公开(公告)日：1988-03-09
申请号：EP87109195.5
申请日：1987-06-26
申请人： Bull HN Information Systems Inc.
发明人： Keeley, James W. , Barlow, George J.
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0859
摘要： A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predeterind state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory. Upon receipt of the requested data, the directory memory is accessed, the RIP memory is reset and the latest data is forwarded to the requesting processing unit as a function of the state of the control means.
摘要翻译：高速缓冲存储器子系统通过与具有相似接口电路的多个中央处理子系统共同的系统总线通过接口电路耦合到主存储器。缓存存储器子系统包括可由至少一对处理单元共享的多级目录存储器和缓冲存储器流水线级。响应于每个读取请求而将与缓冲存储器级相关联的读入（RIP）存储器设置为预取状态，该读取请求产生未命中状态，以识别已预先分配的缓冲存储器中的特定级别的缓冲存储器位置。缓冲存储器级的内容通过响应于由其他子系统应用于系统总线的写请求来更新其内容而与主存储器保持一致。在接收到所请求的数据之后检测到数据的接收将使缓冲存储器内容不连贯，高速缓存切换与RIP存储器相关联的控制装置的状态。在接收到所请求的数据时，访问目录存储器，RIP存储器被重置，并且最新数据作为控制装置的状态的函数转发到请求处理单元。

7. 发明公开

EP0251234A2 Multiprocessor interrupt level change synchronization apparatus 失效转让
标题翻译： Synchronisationsvorrichtungfürdie Interrupt-Ebene-ÄnderungMultiprocessoren。
公开(公告)号：EP0251234A2
公开(公告)日：1988-01-07
申请号：EP87109194.8
申请日：1987-06-26
申请人： Bull HN Information Systems Inc.
发明人： Keeley, James W. , Barlow, George J.
IPC分类号： G06F9/46 , G06F13/26 , G06F15/16
CPC分类号： G06F9/4812 , G06F13/26
摘要： Apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt couples to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.
摘要翻译：装置包括在多处理系统的每个处理单元的总线接口电路中，其与系统的其它单元共同连接到异步系统总线。设备和中断耦合到处理单元的电平寄存器和中断电路。响应于指定电平变化的命令，该设备根据优先级基于处理单元的操作的总线周期期间对这些电路进行条件，以将存储施加到系统总线的电平和中断信号作为这种CPU命令的一部分进行存储。这确保了在不受其他处理单元干扰的情况下中断级别与系统的其他单元的这种电平变化的通知之间的可靠切换。

8. 发明授权

EP0165603B1 Resilient data processing bus system 有权转让
标题翻译：灵活的数据处理总线系统
公开(公告)号：EP0165603B1
公开(公告)日：1993-08-04
申请号：EP85107596.0
申请日：1985-06-19
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Keeley, James W.
IPC分类号： G06F13/42 , G06F11/00
CPC分类号： G06F13/4213 , G06F11/00

9. 发明公开

EP0479229A3 Minimum contention processor and system bus system 失效
标题翻译：最小内存处理器和系统总线系统
公开(公告)号：EP0479229A3
公开(公告)日：1992-09-02
申请号：EP91116755.9
申请日：1991-10-01
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Smith, Donald L.
IPC分类号： G06F13/376
CPC分类号： G06F13/376
摘要： A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.

10. 发明公开

EP0479229A2 Minimum contention processor and system bus system 失效
标题翻译：系统管理员系统总线系统。
公开(公告)号：EP0479229A2
公开(公告)日：1992-04-08
申请号：EP91116755.9
申请日：1991-10-01
申请人： Bull HN Information Systems Inc.
发明人： Barlow, George J. , Smith, Donald L.
IPC分类号： G06F13/376
CPC分类号： G06F13/376
摘要： A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.
摘要翻译：多处理器系统包括多个中央子系统（CSS）单元，多个存储器单元和输入/输出单元，其共同连接到系统总线，用于在由分布式总线优先级定义的优先级基础上在一对单元之间传送请求网络作为系统总线的一部分。专用总线（P总线）将所有的CSS单元和存储单元相连，用于高速块数据传输。每个CSS单元包括耦合到优先网络的输入电路，用于检测系统总线何时处于空闲状态。只有当P总线被检测到处于空闲状态时，P总线逻辑电路才耦合到P总线，并响应于来自其CSS单元的请求而生成传送请求。来自两个总线的空闲信号用于仅在两个总线处于空闲状态时才产生用于P总线访问的系统总线请求，以便消除对系统总线使用的需求。

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