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1. 发明公开

EP0094179A3 Dual path bus structure for computer interconnection 失效
标题翻译：用于计算机互连的双路总线结构
公开(公告)号：EP0094179A3
公开(公告)日：1985-01-30
申请号：EP83302413
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F03/04 , G06F11/22 , G06F11/20 , H04B01/74
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

2. 发明公开

EP0094179A2 Computer interconnection part 失效
标题翻译： AnschluBfürRechnerverbindung。
公开(公告)号：EP0094179A2
公开(公告)日：1983-11-16
申请号：EP83302413.6
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F11/22 , G06F11/20 , G06F13/36 , G06F13/40
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly.
Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput.
Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
摘要翻译：一种用于需要高可用性和通信可靠性的计算机网络中的总线结构。提供多个总线路径（2A，2B）。当要进行传输时，在大多数情况下，随机选择路径，所有路径都是同等可能的。因此，快速检测路径的故障。网络中的每个主机设备通过接口或端口（1）连接到总线路径。路由选择的任务由端口执行，独立于主机设备。这些端口还检测到路径故障，并且在检测到这样的故障时自动切换到备用的良好路径，所有这些都没有主机参与。主机之间的虚拟电路通信对于路径选择和切换是透明的，因此对主机设备进行路径故障的唯一指示是吞吐量的降低。每个端口（10,20A，20B）的信号处理设备的大部分由路径共享，在任何给定时间仅支持一条路径。因此，添加第二总线路径只需要最小的成本。

3. 发明授权

EP0094180B1 Dual-count, round-robin distributed arbitration technique for serial buses 有权
标题翻译：串行总线的双计数RONROBIN分布式仲裁技术
公开(公告)号：EP0094180B1
公开(公告)日：1988-09-07
申请号：EP83302414.4
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Buzynski, John E. , Thompson, David
IPC分类号： H04L11/16 , G06F13/00
CPC分类号： H04L12/40143 , G06F13/368 , G06F13/374 , H04L12/407

4. 发明公开

EP0094180A2 Dual-count, round-robin distributed arbitration technique for serial buses 有权
标题翻译： Stafetten-in-einer-Ringleitung verteiltes Zugriffsverfahrenfürserielle Busse mitDoppelzählung。
公开(公告)号：EP0094180A2
公开(公告)日：1983-11-16
申请号：EP83302414.4
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Buzynski, John E. , Thompson, David
IPC分类号： H04L11/16 , G06F13/00
CPC分类号： H04L12/40143 , G06F13/368 , G06F13/374 , H04L12/407
摘要： An arbitration technique for controlling access to a bit-serial bus (12) by multiple nodes 2(a)-2(n) in a data processing network (1
Upon detection of no carrier on the bus (step 56), a node desiring access to the bus waits a predetermined number of quiet slots (steps 60,64) each slot being a predetermined interval. If that period elapses without another node's carrier being detected (step 64), the node desiring access is permitted to transmit (steps 64, 68). For each node, two such delay interval possibilities are provided, one high slot count (and, hence, low priority) and one low slot count (and, hence, high priority). The delay interval selection for a node is switched from time to time on a round-robin basis, so that all nodes get equal average priority. The high value of the delay interval is N + M + slots, where N is the node number and M is the maximum number of nodes allowed on the bus; the low value is N+ 1 slots.
Initially, each node uses the former value. Upon unsuccessful contention for the bus, the delay interval selection used next by the node depends on the number (LW) of the node which last won access to the bus. Upon detecting a carrier while waiting for access to the bus (i. e., losing arbitration to a higher priority node), the node which is waiting for the bus compares the number of the node (LW) which started transmitting with node number (N) (step 58). If LW was less than N, the node waiting for access uses a new waiting time of N+1 slots the next time the delay interval begins (step 62A); if greater than the node number, the dew delay interval value is N+M+1 slots (step 628).
Provision is made for a multiple path bus wherein much common receiver circuitry is used for the paths. In that situation, if a node's receiver is busy on an alternate path when the node's delay interval expires, the node's delay interval is restarted with a waiting time of M slots assigned to the node.
摘要翻译：一种用于在数据处理网络（1）中由多个节点2（a）-2（n）控制对位串行总线（12）的访问的仲裁技术。在总线上检测到无载波（步骤56）时，要访问总线的节点等待预定数量的安静时隙（步骤60,64），每个时隙是预定间隔。如果在没有检测到另一个节点的载波的情况下经过该时间段（步骤64），则允许访问的节点进行传输（步骤64,68）。对于每个节点，提供两个这样的延迟间隔可能性，一个高时隙计数（因此，低优先级）和一个低时隙计数（并且因此是高优先级）。节点的延迟间隔选择在循环的基础上不时地切换，使得所有节点获得相等的平均优先级。延迟间隔的高值为N + M + 1个时隙，其中N为节点号，M为总线上允许的最大节点数。低值为N + 1个插槽。最初，每个节点使用前一个值。在总线竞争不成功的情况下，下一步由节点使用的延迟间隔选择取决于最后一次访问总线的节点的数量（LW）。在等待接入总线时检测到载波。（即，丢失到较高优先级节点的仲裁），等待总线的节点将开始发送的节点（LW）的数量与节点号（N）进行比较（步骤58）。如果LW小于N，则等待接入的节点在下一次延迟时间间隔开始时使用N + 1个时隙的新的等待时间（步骤62A）; 如果大于节点号，则露点延迟间隔值为N + M + 1个时隙（步骤62B）。提供了一种多路径总线，其中对路径使用多数常见的接收机电路。在这种情况下，如果节点的接收方在节点的延迟时间间隔期满时在备用路径上占线，则节点的延迟时间间隔将重新启动，并将等待时间分配给该节点。

5. 发明授权

EP0282628B1 Dual path bus structure for computer interconnection 失效
标题翻译：用于计算机互连的双路总线结构
公开(公告)号：EP0282628B1
公开(公告)日：1992-07-15
申请号：EP87112180.2
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F13/36
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022

6. 发明公开

EP0282628A3 Dual path bus structure for computer interconnection 失效
标题翻译：计算机互连的双路总线结构
公开(公告)号：EP0282628A3
公开(公告)日：1989-01-25
申请号：EP87112180.2
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F13/36
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

7. 发明授权

EP0094179B1 Computer interconnection part 失效
标题翻译：计算机互连部分
公开(公告)号：EP0094179B1
公开(公告)日：1988-11-09
申请号：EP83302413.6
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F11/22 , G06F11/20 , G06F13/36 , G06F13/40
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022

8. 发明公开

EP0282628A2 Dual path bus structure for computer interconnection 失效
标题翻译： Zweifachbusstrukturfürdie Rechnerverbindung。
公开(公告)号：EP0282628A2
公开(公告)日：1988-09-21
申请号：EP87112180.2
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Thompson, David , Casabona, Richard
IPC分类号： G06F13/36
CPC分类号： G06F11/2007 , G06F11/22 , G06F13/36 , G06F13/4022
摘要： A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly.
Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput.
Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
摘要翻译：一种用于需要高可用性和通信可靠性的计算机网络中的总线结构。提供多个总线路径（2A，2B）。当要进行传输时，在大多数情况下，随机选择路径，所有路径都是同等可能的。因此，快速检测路径的故障。网络中的每个主机设备通过接口或端口（1）连接到总线路径。路由选择的任务由端口执行，独立于主机设备。这些端口还检测到路径故障，并且在检测到这样的故障时自动切换到备用的良好路径，所有这些都没有主机参与。主机之间的虚拟电路通信对于路径选择和切换是透明的，因此对主机设备进行路径故障的唯一指示是吞吐量的降低。每个端口（10,20A，20B）的信号处理设备的大部分由路径共享，在任何给定时间仅支持一条路径。因此，添加第二总线路径只需要最小的成本。

9. 发明公开

EP0094180A3 Dual-count, round-robin distributed arbitration technique for serial buses 有权
标题翻译：串行总线的双计数罗恩分布式仲裁技术
公开(公告)号：EP0094180A3
公开(公告)日：1985-05-08
申请号：EP83302414
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Buzynski, John E. , Thompson, David
IPC分类号： H04L11/16 , G06F03/04
CPC分类号： H04L12/40143 , G06F13/368 , G06F13/374 , H04L12/407
摘要： An arbitration technique for controlling access to a bit-serial bus (12) by multiple nodes 2(a)-2(n) in a data processing network (1 Upon detection of no carrier on the bus (step 56), a node desiring access to the bus waits a predetermined number of quiet slots (steps 60,64) each slot being a predetermined interval. If that period elapses without another node's carrier being detected (step 64), the node desiring access is permitted to transmit (steps 64, 68). For each node, two such delay interval possibilities are provided, one high slot count (and, hence, low priority) and one low slot count (and, hence, high priority). The delay interval selection for a node is switched from time to time on a round-robin basis, so that all nodes get equal average priority. The high value of the delay interval is N + M + slots, where N is the node number and M is the maximum number of nodes allowed on the bus; the low value is N+ 1 slots. Initially, each node uses the former value. Upon unsuccessful contention for the bus, the delay interval selection used next by the node depends on the number (LW) of the node which last won access to the bus. Upon detecting a carrier while waiting for access to the bus (i. e., losing arbitration to a higher priority node), the node which is waiting for the bus compares the number of the node (LW) which started transmitting with node number (N) (step 58). If LW was less than N, the node waiting for access uses a new waiting time of N+1 slots the next time the delay interval begins (step 62A); if greater than the node number, the dew delay interval value is N+M+1 slots (step 628). Provision is made for a multiple path bus wherein much common receiver circuitry is used for the paths. In that situation, if a node's receiver is busy on an alternate path when the node's delay interval expires, the node's delay interval is restarted with a waiting time of M slots assigned to the node.

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