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1. 发明授权

EP0190370B1 Device for improving the detection of non-operational states in a non-attended interrupt-driven processor 失效
标题翻译：用于改善在非参与式中断处理器中检测非操作状态的设备
公开(公告)号：EP0190370B1
公开(公告)日：1990-04-04
申请号：EP84430050.9
申请日：1984-12-31
申请人： International Business Machines Corporation , Compagnie IBM FRANCE
发明人： Combes, Jacques , Robbe, Jean-Claude , Viallon, Paul
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/22 , G06F11/0757

2. 发明公开

EP0190370A1 Device for improving the detection of non-operational states in a non-attended interrupt-driven processor 失效
标题翻译：装置用于在非操作中断驱动的处理器检测出服务状态中的。
公开(公告)号：EP0190370A1
公开(公告)日：1986-08-13
申请号：EP84430050.9
申请日：1984-12-31
申请人： International Business Machines Corporation , Compagnie IBM FRANCE
发明人： Combes, Jacques , Robbe, Jean-Claude , Viallon, Paul
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/22 , G06F11/0757
摘要： Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching an unoperational state detection task running on the n-1 priority level at time intervals smallerthan a specified time-out delay. A detection timer (1) which is set at an initial value each time the task is dispatched and the content of which is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and which are reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.

3. 发明授权

EP0849917B1 Switching system 失效
标题翻译：交换系统
公开(公告)号：EP0849917B1
公开(公告)日：2005-07-20
申请号：EP97480056.7
申请日：1997-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Blanc, Alain , Robbe, Jean-Claude , Landry, Christian , Poret, Michel
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/203 , H04L49/309 , H04L2012/5625 , H04L2012/563 , H04L2012/5652 , H04L2012/5681

4. 发明授权

EP0961442B1 Switching architecture comprising two switch fabrics 失效
标题翻译：交换架构与耦合双Felden
公开(公告)号：EP0961442B1
公开(公告)日：2004-09-29
申请号：EP98480039.1
申请日：1998-05-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Blanc, Alain , Brezzo, Bernard , Robbe, Jean-Claude , Gohl, Sylvie , Saurel, Alain
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/309 , H04L49/455 , H04L2012/5627 , H04L2012/5647

5. 发明公开

EP0961442A1 Switching architecture comprising two switch fabrics 失效
标题翻译： Vermittlungsarchitektur mit zwei Koppelfelden
公开(公告)号：EP0961442A1
公开(公告)日：1999-12-01
申请号：EP98480039.1
申请日：1998-05-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Blanc, Alain , Brezzo, Bernard , Robbe, Jean-Claude , Gohl, Sylvie , Saurel, Alain
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/309 , H04L49/455 , H04L2012/5627 , H04L2012/5647
摘要： A Switching architecture comprising a first and a second Switch Fabrics (10, 20) including a switch core (15, 25) located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element respectively comprises a SCAL Receive element (11-i) and a SCAL Xmit element (12-i) for respectively permitting access to a corresponding input and output port of the switch core. The Port Adapters (30; 31) are distributed at different physical areas and each one is connected to the first and second Switch Fabric via a particular SCAL element so that each Switch core (15, 25) receives the sequence of cells coming from any Port adapter and conversely any Port adapter may receive data from any one of said first or second switch core. There are arranged means (15, 100) for assigning a particular Switch core to any Port adapter for the normal traffic of cells and for reserving the other switch core to Backup or maintenance traffic situations. To achieve this each switch core is fitted with a masking mechanism which uses the value loaded into a Mask register for altering the bitmap value which is normally used inside the switch core for controlling the routing process. Since the Mask registers in the two switch cores are loaded with complementary values, this permits a perfect distribution of the cells via one and only one SCAL Xmit element towards any Port Adapter. Preferably the Mask mechanism can be controlled by a special control field located into the cell, or when maintenance of backup conditions are planned.
摘要翻译：一种交换架构，包括第一和第二交换矩阵（10,20），其包括位于集中式建筑物中的交换核心（15,25）和分布在不同物理区域中的一组SCAL元件。每个SCAL元件分别包括用于分别允许访问交换机核心的相应输入和输出端口的SCAL接收元件（11-i）和SCAL Xmit元件（12-i）。端口适配器（30; 31）分布在不同的物理区域，并且每个通过特定的SCAL元件连接到第一和第二交换结构，使得每个交换机内核（15,25）接收来自任何端口的单元序列适配器，并且相反，任何端口适配器可以从所述第一或第二交换机核心中的任何一个接收数据。布置了用于将特定交换机核心分配给用于小区正常业务的任何端口适配器并用于将另一交换机核心保留到备份或维护业务情况的装置（15,100）。为了实现这一点，每个交换机核心都配有一个掩蔽机制，该机制使用加载到掩码寄存器中的值来改变通常用于控制路由过程的交换机核心内的位图值。由于两个交换机核心中的掩码寄存器都加载了互补值，因此允许通过一个且仅一个SCAL Xmit元素将单元格完美分配给任何端口适配器。优选地，掩模机构可以由位于单元中的特定控制区域或者在计划备用条件的维护时进行控制。

6. 发明授权

EP0288650B1 Protocol and apparatus for a control link between a control unit and several devices 失效
标题翻译：控制单元和几个设备之间的控制链路的协议和设备
公开(公告)号：EP0288650B1
公开(公告)日：1992-07-08
申请号：EP87430016.3
申请日：1987-04-28
申请人： International Business Machines Corporation
发明人： Robbe, Jean-Claude , Munier, Jean-Marie , Poret, Michel
IPC分类号： G06F13/42
CPC分类号： G06F13/423

7. 发明公开

EP0288650A1 Protocol and apparatus for a control link between a control unit and several devices 失效
标题翻译：协议和装置的控制单元和多个外围元件之间的连接。
公开(公告)号：EP0288650A1
公开(公告)日：1988-11-02
申请号：EP87430016.3
申请日：1987-04-28
申请人： International Business Machines Corporation
发明人： Robbe, Jean-Claude , Munier, Jean-Marie , Poret, Michel
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： A Device control link (DCL) and its protocol of operation, especially adapted for safe transmission of control signals between a control unit (10) and devices (18), such as adapters connected to the Control Unit.
The Control Unit is linked to the devices by a dedicated request line (30) per device, a dot-ORed acknowledge line (32), at least one clock line (38) transmitting sets of N clock pulses from the Control Unit to a device during each data exchange, and two data lines (34,36) for serial duplex data transmission.
The Control Unit and each device include an N-bits shift register, and the data line (34,36) connects the N-bits shift register (42) of the Control Unit to the N-bits shift register (44) of a selected device so as to form, upon receipt of a request, a loop (74) allowing data exchanges between said shift registers.
The data exchange protocol comprises two phases, the second phase being started only if the first one has been completed without errors.
During each phase, N information (data, commands, status) bits are exchanged between the Control Unit and a determined device.
摘要翻译：一种设备控制链路（DCL）和其操作的协议，爱对于控制单元（10）和装置（18）之间的控制信号的安全传输特别angepasst：诸如连接到控制单元的适配器。所述控制单元被通过每设备的专用请求线（30）连接至设备，一个点或运算确认线（32），至少一个时钟线（38）发送台从控制单元N个时钟脉冲的到设备每个数据交换期间，以及用于串行双工数据传输的两个数据线（34,36）。在控制单元和每个设备包括N位的移位寄存器，以及数据线（34,36）的选定的控制单元的N比特移位寄存器（42）连接到所述N位的移位寄存器（44）设备，以便形成，在接收到请求时，一个环（74）使所述移位寄存器之间的数据交换。数据交换协议包括两个阶段，只有当第一个已被无错完成第二阶段被启动。在每个阶段，N个信息（数据，命令，状态）位控制单元和一个确定的开采设备之间交换。

8. 发明公开

EP0849917A3 Switching system 失效
标题翻译：交换系统
公开(公告)号：EP0849917A3
公开(公告)日：1998-12-16
申请号：EP97480056.7
申请日：1997-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Blanc, Alain , Robbe, Jean-Claude , Landry, Christian , Poret, Michel
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/203 , H04L49/309 , H04L2012/5625 , H04L2012/563 , H04L2012/5652 , H04L2012/5681
摘要： A switching module including a storage section that comprises a set of M receiver means (10), a set of M input routers (2) for realizing the connection of the M input ports to anyone of the different locations of a cell storage (1). The storage section includes a set of M ASA registers (20, 21) for providing to input routers (2) with the addresses to be used for storing the cells into the cell storage (1). Additionaly, the switching module includes a retrieve section that comprises a set of M output routers for retrieving the data located into any locations of said cell storage (1), a set of M ARA registers for providing to said output routers (3) the addresses of the cells which are to be outputted from said cell storage. Further, a specific control section provides with the input process and the output process of the cells that are entered into the switch. The input control section address generating means (FAQ 5) for providing the addresses of the empty locations into cell storage (1) and first multiplexing means (106, 107, 112, 113) for providing either the addresses generated by said address generating means (FAQ 5) or addresses provided by a first external bus (509, 510) to said M ASA registers (20, 21). A set of holding registers (60, 63) is used for retaining the module routing header as long as the cells are being inputted in the cell storage (1). The output control section comprises a set of M queueing means (OAQ 50, 51) for queueing the addresses of the locations within said cell storage (1) that contains cells that are to be transmitted to output ports. Each queuing means has an input receiving the contents of said ASA registers (20, 21) and is associated to a corresponding one of said M output ports. Additionaly control means (150, 200) receive the module routing header retained by the holding registers and generate control signals (WEs, 210) for all the queuing means (50, 51) so that the contents of said ASA registers can be simultaneously loaded into the particular queuing means (OAQ queues 50, 51) that corresponds to the ouput ports according to the module routing header, that is to say in accordance with the particular output ports to which the cell should be duplicated. Second multiplexing means (800, 26, 27) are provided so as to provide to said M ARA registers either with addresses provided by the queuing means (OAQ 50, 51) or the addresses provided by a second external bus (520, 521). A specific registration circuit (7) is used for preventing an address into cell storage (1) to be made available as long as the last occurence of the considered address disappear from the contents of the queuing means. By means ofthe first and second multiplexor it becomes possible to realize the routing process internally or externally. Indeed, the addresses that are used for performing both the input and output process may either be generated by means of the internally located circuits, including the addresses generating means and control circuit (200), or still may be achieved by means of an external circuitry (with the respect to the module being considered).
摘要翻译：一种包括存储部分的交换模块，该存储部分包括一组M个接收器装置（10），一组M个输入路由器（2），用于实现将M个输入端口连接到单元存储器（1）的不同位置中的任何一个，。存储部分包括一组M ASA寄存器（20,21），用于向输入路由器（2）提供要用于将信元存储到信元存储器（1）中的地址。另外，切换模块包括：检索部分，其包括用于检索位于所述单元存储器（1）的任何位置的数据的一组M个输出路由器，用于向所述输出路由器（3）提供地址的一组MARA寄存器将从所述细胞存储器输出的细胞。此外，特定的控制部分提供输入到开关中的单元的输入过程和输出过程。用于将空位置的地址提供给单元存储器（1）的输入控制部分地址产生装置（FAQ 5）和第一多路复用装置（106,107,112,113），用于提供由所述地址产生装置（（5）或由第一外部总线（509,510）提供给所述M个ASA寄存器（20,21）的地址。只要单元正被输入到单元存储器（1）中，一组保持寄存器（60,63）用于保持模块路由头。输出控制部分包括一组M个排队装置（OAQ 50,51），用于排队所述单元存储器（1）内包含将被发送到输出端口的单元的位置的地址。每个排队装置具有接收所述ASA寄存器（20,21）的内容并且与所述M个输出端口中对应的一个输出端口相关联的输入。附加控制装置（150,200）接收由保持寄存器保持的模块路由报头并为所有排队装置（50,51）产生控制信号（WEs，210），使得所述ASA寄存器的内容可以同时加载到根据模块路由报头，也就是说根据应该复制单元的特定输出端口，对应于输出端口的特定排队装置（OAQ队列50,51）。提供第二多路复用装置（800,26,27），以便向所述M个ARA寄存器提供由排队装置（OAQ 50,51）提供的地址或由第二外部总线（520,521）提供的地址。只要所考虑的地址的最后一次出现从排队装置的内容中消失，就使用特定的登记电路（7）来防止地址进入单元存储（1）。通过第一和第二多路复用器，可以在内部或外部实现路由选择过程。事实上，用于执行输入和输出过程的地址可以通过包括地址生成装置和控制电路（200）的内部定位电路来生成，或者仍然可以通过外部电路（关于正在考虑的模块）。

9. 发明公开

EP0849917A2 Switching system 失效
标题翻译： Vermittlungssystem
公开(公告)号：EP0849917A2
公开(公告)日：1998-06-24
申请号：EP97480056.7
申请日：1997-08-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Blanc, Alain , Robbe, Jean-Claude , Landry, Christian , Poret, Michel
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/203 , H04L49/309 , H04L2012/5625 , H04L2012/563 , H04L2012/5652 , H04L2012/5681
摘要： A switching module including a storage section that comprises a set of M receiver means (10), a set of M input routers (2) for realizing the connection of the M input ports to anyone of the different locations of a cell storage (1). The storage section includes a set of M ASA registers (20, 21) for providing to input routers (2) with the addresses to be used for storing the cells into the cell storage (1). Additionaly, the switching module includes a retrieve section that comprises a set of M output routers for retrieving the data located into any locations of said cell storage (1), a set of M ARA registers for providing to said output routers (3) the addresses of the cells which are to be outputted from said cell storage.
Further, a specific control section provides with the input process and the output process of the cells that are entered into the switch. The input control section address generating means (FAQ 5) for providing the addresses of the empty locations into cell storage (1) and first multiplexing means (106, 107, 112, 113) for providing either the addresses generated by said address generating means (FAQ 5) or addresses provided by a first external bus (509, 510) to said M ASA registers (20, 21). A set of holding registers (60, 63) is used for retaining the module routing header as long as the cells are being inputted in the cell storage (1).
The output control section comprises a set of M queueing means (OAQ 50, 51) for queueing the addresses of the locations within said cell storage (1) that contains cells that are to be transmitted to output ports. Each queuing means has an input receiving the contents of said ASA registers (20, 21) and is associated to a corresponding one of said M output ports. Additionaly control means (150, 200) receive the module routing header retained by the holding registers and generate control signals (WEs, 210) for all the queuing means (50, 51) so that the contents of said ASA registers can be simultaneously loaded into the particular queuing means (OAQ queues 50, 51) that corresponds to the ouput ports according to the module routing header, that is to say in accordance with the particular output ports to which the cell should be duplicated. Second multiplexing means (800, 26, 27) are provided so as to provide to said M ARA registers either with addresses provided by the queuing means (OAQ 50, 51) or the addresses provided by a second external bus (520, 521). A specific registration circuit (7) is used for preventing an address into cell storage (1) to be made available as long as the last occurence of the considered address disappear from the contents of the queuing means.
By means ofthe first and second multiplexor it becomes possible to realize the routing process internally or externally. Indeed, the addresses that are used for performing both the input and output process may either be generated by means of the internally located circuits, including the addresses generating means and control circuit (200), or still may be achieved by means of an external circuitry (with the respect to the module being considered).
摘要翻译：一种切换模块，包括存储部分，所述存储部分包括一组M个接收装置（10），一组M个输入路由器（2），用于实现M个输入端口连接到小区存储装置（1）的不同位置的任意一个，。存储部分包括一组M ASA寄存器（20,21），用于向输入路由器（2）提供要用于将单元存储到单元存储器（1）中的地址。另外，切换模块包括检索部分，其包括用于检索位于所述小区存储（1）的任何位置的数据的一组M个输出路由器，一组M ARA寄存器，用于向所述输出路由器（3）提供地址将要从所述单元存储器输出的单元。此外，特定控制部分提供输入到开关中的单元的输入处理和输出处理。用于将空位置的地址提供到单元存储器（1）的输入控制区地址生成装置（FAQ5）和用于提供由所述地址生成装置生成的地址的第一多路复用装置（106,107,112,113）常见问题5）或由第一外部总线（509,510）提供给所述M ASA寄存器（20,21）的地址。一组保持寄存器（60,63）用于保持模块路由头部，只要这些单元被输入到单元存储器（1）中即可。输出控制部分包括一组M排队装置（OAQ 50,51），用于对包含要发送到输出端口的单元的所述单元存储器（1）内的位置的地址进行排队。每个排队装置具有接收所述ASA寄存器（20,21）的内容的输入，并且与所述M个输出端口中相应的一个相关联。附加控制装置（150,200）接收由保持寄存器保留的模块路由报头，并为所有排队装置（50,51）生成控制信号（WEs，210），使得所述ASA寄存器的内容可以同时加载到根据模块路由头，即根据应该复制小区的特定输出端口，对应于输出端口的特定排队装置（OAQ队列50,51）。提供第二复用装置（800,26,27），以便向所述M ARA寄存器提供由排队装置（OAQ 50,51）提供的地址或由第二外部总线（520,521）提供的地址。只要所考虑的地址的最后一次出现从排队装置的内容中消失，特定的注册电路（7）用于防止地址进入小区存储（1）。通过第一和第二多路复用器，可以在内部或外部实现路由过程。实际上，用于执行输入和输出处理的地址可以通过内部定位的电路（包括地址产生装置和控制电路（200））产生，或者仍然可以通过外部电路（相对于正在考虑的模块）。

10. 发明公开

EP0505651A1 Mechanism for controlling the resources of a distributed information processing system 失效
标题翻译： Vorrichtung zum Steuern von Betriebsmitteln eines verteilten Informationsverarbeitungssystems。
公开(公告)号：EP0505651A1
公开(公告)日：1992-09-30
申请号：EP91480051.1
申请日：1991-03-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brezzo, Bernard , Calvignac, Jean-Louis , Munier, Jean-Marie , Naudin, Bernard, "les Provencales" , Robbe, Jean-Claude
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4004 , G06F13/385 , G06F13/4031
摘要： A data processing system includes data processing adapters (2) for controlling the data transfers between end systems (1) and a memory through contention type busses (7 and 11) and a control processor connected to the system bus (7) for through a coupler (8) for controlling the physical resources such as registers or memories of the whole data processing system. A control operation is initiated by the control processor which presents on its processor bus (14) a control operation to be executed in a destination unit which can be the coupler, a selected data processing adapter or a selected end system. Each unit is provided with a control operation interface dedicated to the processing of the control operation or its forwarding toward the destination unit and the preparation of a response to the control operation in the destination unit and the propagation of the response toward the coupler, so as to minimize the bus occupancy times.
摘要翻译：数据处理系统包括用于通过竞争型总线（7和11）控制终端系统（1）和存储器之间的数据传输的数据处理适配器（2）和连接到系统总线（7）的控制处理器，用于通过耦合器（8），用于控制诸如整个数据处理系统的寄存器或存储器的物理资源。由控制处理器启动控制操作，控制处理器在其处理器总线（14）上呈现要在可以是耦合器，所选数据处理适配器或选定端系统的目的地单元中执行的控制操作。每个单元设置有专用于处理控制操作或其向目的地单元的转发的控制操作界面以及对目的地单元中的控制操作的响应的准备以及响应朝向耦合器的传播，从而以最小化公交车的占用时间。

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