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51. 发明公开

EP1986234A3 Power semiconductor module for inverter circuit system 有权转让
标题翻译：用于逆变器电路系统的功率半导体模块
公开(公告)号：EP1986234A3
公开(公告)日：2012-01-25
申请号：EP08006762.2
申请日：2008-04-02
申请人： Hitachi, Ltd.
发明人： Tokuyama, Takeshi , Nakatsu, Kinya , Saito, Ryuichi
IPC分类号： H01L25/07 , H01L25/11 , H01L23/40
CPC分类号： H01L25/115 , H01L23/473 , H01L25/072 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H02M7/003 , H02M7/81 , H05K7/20927 , H01L2924/00014 , H01L2924/00
摘要： A double-face-cooled semiconductor module (500) with an upper arm and a lower arm of an inverter circuit (44) includes first and second heat dissipation members (522, 562), each having a heat dissipation surface on one side and a conducting member (534) formed on another side through an insulation member (524). On the conducting member (534) on the first dissipation plate is provided with a fixing portion (536) that fixes a collector surface of the semiconductor chip (538, 547) and a gate conductor connected to a gate terminal (553) of the semiconductor module. The gate electrode terminal and the gate conductor (555) are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.

52. 发明公开

EP1959719A2 Power converter 有权
标题翻译：电源转换器
公开(公告)号：EP1959719A2
公开(公告)日：2008-08-20
申请号：EP08001451.7
申请日：2008-01-25
申请人： Hitachi, Ltd.
发明人： Nakamura, Takayoshi , Nakatsu, Kinya , Miyazaki, Hideki , Saito, Ryuichi
IPC分类号： H05K7/20 , H05K7/14
CPC分类号： H05K7/20927 , H01L2224/48472 , H01L2224/49111 , H01L2924/19107
摘要： According to the present invention, a power converter (100) includes at least two power semiconductor modules (101) having a plurality of switching devices, at least two cooling jackets (205) having a coolant path for cooling the.plurality of power semiconductor modules (101) and equipped with the power semiconductor modules (101), a capacitor module (102) interposed between the at least two cooling jackets (205), and a connector (240) provided in the at least two cooling jackets (205) for connecting the coolant path.
A compact power converter with improved productivity and improved flexibility in cooling electronic parts can be provided.
摘要翻译：根据本发明，功率转换器（100）包括具有多个开关装置的至少两个功率半导体模块（101），至少两个具有冷却剂路径的冷却套（205），用于冷却多个功率半导体模块（205）上的电容器模块（102）以及设置在所述至少两个冷却套（205）中的连接器（240），所述连接器（101）具有功率半导体模块（101）连接冷却剂路径。可以提供具有提高的生产率和改进的冷却电子部件的灵活性的紧凑型功率转换器。

53. 发明公开

EP1492220A2 IGBT-module 失效
标题翻译： Leistungswandler und in diesem verwendbares Halbleitermodul
公开(公告)号：EP1492220A2
公开(公告)日：2004-12-29
申请号：EP04021377.9
申请日：1992-09-17
申请人： Hitachi, Ltd.
发明人： Mori, Mutsuhiro , Saito, Ryuichi , Kimura, Shin , Nakata, Kiyoshi , Saitoo, Syuuji , Horie, Akira , Koike, Yoshihiko , Sekine, Shigeki
IPC分类号： H02M7/48 , H01L23/538 , H01L25/07
CPC分类号： H03K17/08148 , H01L23/04 , H01L23/18 , H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/072 , H01L25/16 , H01L25/18 , H01L29/66333 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01055 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/19041 , H01L2924/30107 , H01L2924/351 , H02M7/003 , H02M7/487 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： An IGBT module including a plurality of IGBT single modules each having a plurality of IGBT chips (31a, 31b), a diode chip (32a, 32b), an emitter terminal (E1; E2) and a collector terminal (C1; C2), these being disposed on one surface of an insulation plate (11a; 11b) through electrode plates (12a, 12b), a metal substrate (20) mounting the isolation plates (11a, 11b) of the plurality of IGBT single modules on one surface and a resin case (50) bonded on the surface of said metal substrate (20) and incorporating said IGBT single module. According to the invention the emitter terminals (E1, E2) and the collector terminals (C1, C2) of said plurality of IGBT single modules are exposed on an upper surface of said resin case (50), the emitter terminals (E1, E2) are disposed side by side on a straight line parallel with and near the front edge of said metal substrate (20), the collector terminals (C1) are disposed side by side on a straight line parallel with the straight line on which said emitter terminals (E1; E2) are disposed, and at least one protruding part (21a) is formed on the upper surface of said resin case (50) for delimiting said emitter terminals (E1, E2) from said collector terminals (C1, C2).
摘要翻译：一种IGBT模块，包括多个IGBT单个模块，每个具有多个IGBT芯片（31a，31b），二极管芯片（32a，32b），发射极端子（E1; E2）和集电极端子（C1; C2）它们通过电极板（12a，12b）设置在绝缘板（11a; 11b）的一个表面上，金属基板（20）将多个IGBT单模块的隔离板（11a，11b）安装在一个表面上，结合在所述金属基板（20）的表面上并结合有所述IGBT单模块的树脂壳体（50）。根据本发明，所述多个IGBT单模块的发射极端子（E1，E2）和集电极端子（C1，C2）暴露在所述树脂壳体（50）的上表面上，发射极端子（E1，E2）并排设置在与所述金属基板（20）的前边缘平行并且靠近所述金属基板（20）的直线上的直线上，所述集电极端子（C1）并排设置在与所述发射极端子 E1; E2），并且至少一个突出部分（21a）形成在所述树脂箱（50）的上表面上，用于限定所述发射极端子（E1，E2）与所述集电端子（C1，C2）的距离。

55. 发明公开

EP1024498A3 Semiconductor memory device and method of operation 失效
标题翻译：半导体存储器件和操作方法
公开(公告)号：EP1024498A3
公开(公告)日：2002-05-08
申请号：EP00106044.1
申请日：1991-08-02
申请人： Hitachi, Ltd.
发明人： Saito, Ryuichi , Kobayashi, Yutaka , Onose, Hidekatsu , Ohue, Michio
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C8/14 , G11C11/22 , G11C11/5657 , G11C16/08 , H01L27/10805
摘要： A semiconductor memory device has a plurality of memory cells (351,352,353,354) in an array, into which the memory cells (351,352,353,354) data is writable, and which can subsequently be read. Each memory cell has a switching element (111) with one terminal connected to a bit line (120) of the array another terminal connected to at least one ferroelectric capacitor (112,113,114,115), and a control terminal connected to a word line (121). The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor (427) and a capacitor (428) other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality (112,113,114,115) of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.
摘要翻译：半导体存储器件具有阵列中的多个存储器单元（351,352,353,354），存储器单元（351,352,353,354）中的数据是可写的，并且随后可被读取。每个存储器单元具有开关元件（111），其一端连接到阵列的位线（120），另一端连接到至少一个铁电电容器（112,113,114,115），并且控制端连接到字线（121）。然后可以操作该单元以检测当施加不足以引起铁电电容器的状态变化的电压时铁电电容器的极化变化。或者，在开关元件上连接强电介质电容器（427）和铁电电容器以外的电容器（428）。在进一步的替代方案中，多个（112,113,114,115）铁电电容器连接到开关元件，使得不同的数据可写入每个中。

56. 发明公开

EP1024497A3 Semiconductor memory device and method of operation 失效
标题翻译：操作的方法和装置的半导体存储器的
公开(公告)号：EP1024497A3
公开(公告)日：2002-05-08
申请号：EP00106043.3
申请日：1991-08-02
申请人： Hitachi, Ltd.
发明人： Saito, Ryuichi , Kobayashi, Yutaka , Onose, Hidekatsu , Ohue, Michio
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C8/14 , G11C11/22 , G11C11/5657 , G11C16/08 , H01L27/10805
摘要： A semiconductor memory device has a plurality of memory cells (351,352,353,354) in an array, into which the memory cells (351,352,353,354) data is writable, and which can subsequently be read. Each memory cell has a switching element (111) with one terminal connected to a bit line (120) of the array another terminal connected to at least one ferroelectric capacitor (112,113,114,115), and a control terminal connected to a word line (121). The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor (427) and a capacitor (428) other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality (112,113,114,115) of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

57. 发明公开

EP1024499A3 Semiconductor memory device and method of operation 失效
公开(公告)号：EP1024499A3
公开(公告)日：2002-05-02
申请号：EP00106045.8
申请日：1991-08-02
申请人： Hitachi, Ltd.
发明人： Saito, Ryuichi , Kobayashi, Yutaka , Onose, Hidekatsu , Ohue, Michio
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C8/14 , G11C11/22 , G11C11/5657 , G11C16/08 , H01L27/10805
摘要： A semiconductor memory device has a plurality of memory cells (351,352,353,354) in an array, into which the memory cells (351,352,353,354) data is writable, and which can subsequently be read. Each memory cell has a switching element (111) with one terminal connected to a bit line (120) of the array another terminal connected to at least one ferroelectric capacitor (112,113,114,115), and a control terminal connected to a word line (121). The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor (427) and a capacitor (428) other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality (112,113,114,115) of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

58. 发明公开

EP0838855A3 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：EP0838855A3
公开(公告)日：1998-07-29
申请号：EP97122703.8
申请日：1992-09-17
申请人： Hitachi, Ltd.
发明人： Mori, Mutsuhiro , Saito, Ryuichi , Kimura, Shin , Nakata, Kiyoshi , Saitoo, Syuuji , Horie, Akira , Koike, Yoshihiko , Sekine, Shigeki
IPC分类号： H01L25/065 , H02M7/48
CPC分类号： H03K17/08148 , H01L23/04 , H01L23/18 , H01L23/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/072 , H01L25/16 , H01L25/18 , H01L29/66333 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01055 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/19041 , H01L2924/30107 , H01L2924/351 , H02M7/003 , H02M7/487 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor module comprising a plurality of switching device chips (35) disposed on a metal substrate (30) are provided with main electrodes (35C, 35E) on the main surfaces of the chips (35) and a control electrode (35G); at least one diode chip (36) disposed on the metal substrate (30) is provided with main electrodes (36A, 35K) on the main surface of said chip (36); an electrode plate (31) disposed on the metal substrate (30) through an insulation plate (32a) and connected with a plurality of conductive portions of the other main electrodes of the switching device chip (35) and the diode chip (36); first and second lead terminals for connecting the one main electrode (35C) of the switching device chip (35) with the one main electrode (36A) of the diode chip (36), and a resin case (103) for covering the module, wherein the first and second lead terminals are brought out to an outside of the resin case.
摘要翻译：包括设置在金属衬底（30）上的多个开关器件芯片（35）的半导体模块在芯片（35）的主表面和控制电极（35G）上设置有主电极（35C，35E）; 设置在金属基板（30）上的至少一个二极管芯片（36）在所述芯片（36）的主表面上设置有主电极（36A，35K）; 通过绝缘板（32a）设置在金属基板（30）上并与开关器件芯片（35）和二极管芯片（36）的另一主电极的多个导电部分连接的电极板（31）; 用于连接开关器件芯片（35）的一个主电极（35C）与二极管芯片（36）的一个主电极（36A）的第一和第二引线端子以及用于覆盖模块的树脂壳体（103）其中第一和第二引线端子被引出到树脂外壳的外部。

60. 发明公开

EP0828341A2 Modular type power semiconductor apparatus 失效
标题翻译： Bauart模型中的Leistungshalbleiteranordnung
公开(公告)号：EP0828341A2
公开(公告)日：1998-03-11
申请号：EP97115291.3
申请日：1997-09-02
申请人： HITACHI, LTD. , Hitachi Kyowa Engineering Co., Ltd.
发明人： Tanaka, Akira , Inoue, Hirokazu , Kushima, Tadao , Koike, Yoshihiko , Shimizu, Hideo , Saito, Ryuichi , Suzuki, Kazuhiro , Kurihara, Yasutoshi , Okada, Sensuke , Koizumi, Masahiro , Kajiwara, Ryoichi , Sonobe, Yukio , Nakatsu, Kinya , Kuribayashi, Shigehisa
IPC分类号： H02M7/00 , H01L25/07
CPC分类号： H01L24/06 , H01L23/49861 , H01L23/5385 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/0401 , H01L2224/451 , H01L2224/48 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/13055 , H01L2924/181 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H02M7/003 , H01L2924/00015 , H01L2224/05599 , H01L2924/00
摘要： An IGBT unit of a power semiconductor module which comprises a plurality of insulation substrates each of which mounting a plurality of semiconductor devices thereon which are to be operated in parallel within the module is provided. External terminals corresponding to each unit are disposed outside the module for parallel operation thereof, thereby minimizing inductance between respective semiconductor devices and their wirings.
摘要翻译：提供了一种功率半导体模块的IGBT单元，其包括多个绝缘基板，每个绝缘基板在其内部安装要在模块内并联操作的多个半导体器件。对应于每个单元的外部端子设置在模块外部用于其并联操作，从而最小化各个半导体器件及其布线之间的电感。

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