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41. 发明授权

EP0547240B1 RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE 失效
标题翻译：具有快速中断或异常模式RISC微处理器架构
公开(公告)号：EP0547240B1
公开(公告)日：2000-01-12
申请号：EP92914386.5
申请日：1992-07-07
申请人： SEIKO EPSON CORPORATION
发明人： NGUYEN, Le Trong , LENTZ, Derek, J. , MIYAYAMA, Yoshiyuki , GARG, Sanjiv , HAGIWARA, Yasuaki , WANG, Johannes , TRANG, Quang, H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812 , G06F15/7842
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.

42. 发明公开

EP0772123A3 Data processing system with instruction prefetch 失效
标题翻译：包括Befehlsvorausholung数据处理系统
公开(公告)号：EP0772123A3
公开(公告)日：1999-05-12
申请号：EP96307778.9
申请日：1996-10-28
申请人： International Business Machines Corporation
发明人： Mayfield, Michael J.
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/383 , G06F12/0862 , G06F12/0897
摘要： A method for selectively prefetching a cache line into a primary instruction cache within a processor from main memory allows for cold cache instruction prefetching of additional cache lines when the requested cache line does not reside within either the primary or secondary cache associated with the processor and there are no unresolved branches associated with the requested instruction in the cache line.

43. 发明授权

EP0592404B1 APPARATUS AND METHOD FOR PROVIDING A STALL CACHE 失效
标题翻译：方法和装置用于阻挡CACHE是必要的
公开(公告)号：EP0592404B1
公开(公告)日：1998-09-16
申请号：EP91906378.4
申请日：1991-02-28
申请人： SUN MICROSYSTEMS, INC.
发明人： FRANK, Edward, H. , NAMJOO, Masood
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381 , G06F9/3824
摘要： A computer processor (32) which utilizes a very small on-chip cache (46) for storing only those instructions which are not accessed because of a data access on the data bus (36) occurring during a load or a store instruction whereby the instruction is available to the processor upon the next data access during such an instruction without the delay of a bus access.

44. 发明公开

EP0772820A1 TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS 失效
标题翻译：两级预制缓冲结构和带旁路的方法
公开(公告)号：EP0772820A1
公开(公告)日：1997-05-14
申请号：EP96914775.0
申请日：1996-05-23
申请人： National Semiconductor Corporation
发明人： DIVIVIER, Robert, J. , NEMIROVSKY, Mario , WILLIAMS, Robert
IPC分类号： G06F9
CPC分类号： G06F9/3814 , G06F9/3802
摘要： A method and apparatus for prefetching instructions in a pipelined processor including first and second prefetch buffers arranged in a two tier system. As instruction bytes are fetched from cache memory or external memory, those instruction bytes from memory for which there is space in the first level buffer are loaded therein, and, simultaneously, those valid instruction bytes in the second tier buffer for which there is room in the first tier buffer are also loaded into the first tier buffer. Those instruction bytes from memory for which there is not currently room in the first tier buffer are loaded into the second tier buffer. The second tier buffer is also used as a buffer for loading the instruction cache memory from the external memory.
摘要翻译：一种用于在流水线处理器中预取指令的方法和装置，所述流水线处理器包括以双层系统排列的第一和第二预取缓冲器。由于指令字节是从高速缓冲存储器或外部存储器中取出的，因此在第一级缓冲区中有来自空间的存储器中的这些指令字节被加载到其中，并且同时，第二层缓冲区中有空间的那些有效指令字节第一层缓冲区也被加载到第一层缓冲区中。来自存储器的第一层缓冲区中当前没有空间的那些指令字节被加载到第二层缓冲区中。第二层缓冲区也用作从外部存储器加载指令缓冲存储器的缓冲区。

45. 发明授权

EP0476722B1 Data processing system 失效
公开(公告)号：EP0476722B1
公开(公告)日：1997-02-26
申请号：EP91120043.4
申请日：1986-04-08
申请人： HITACHI, LTD.
发明人： Kida, Hiroyuki , Maejima, Hideo , Masuda, Ikuro , Baba, Shirou
IPC分类号： G06F9/46
CPC分类号： G06F9/462 , G06F8/41 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30196 , G06F9/3814 , G06F9/3851 , G06F9/4486
摘要： The instruction word memory (301) stores the different instruction functions for each binary instruction code. A respective instruction decoder (302,502) is provided for each instruction function system. The resulting codes are passed over a respective bus (3021,5021) to a multiplexer (303). A flip-flop (504) controls operation of the multiplexer to cause selection of the bus for input to the multiplexer. One instruction decoder extracts information in one-to-one correspondance to inputs of another instruction decoder from the instruction word. The information is stored. The other decoder is operative to invalidate outputs using a microinstruction output from the microprogram memory.

46. 发明公开

EP0732656A2 Cache MMU system 失效
标题翻译：缓存MMU系统
公开(公告)号：EP0732656A2
公开(公告)日：1996-09-18
申请号：EP96108915.8
申请日：1986-02-21
申请人： Intergraph Corporation
发明人： Sachs, Howard Gene , Hollingsworth, Walter H. , Cho, James Youngsae
IPC分类号： G06F12/08
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0831 , G06F12/0848 , G06F12/0862 , G06F12/0864 , G06F12/1054
摘要： A cache and memory management system architecture and associated protocol is disclosed. The cache and memory management system is comprised of a set associative memory cache subsystem, a set associative translation logic memory subsystem, hardwired page translation, selectable access mode logic, and selectively enablable instruction prefetch logic. The cache and memory management system includes a system interface for coupling to a systems bus to which a main memory is coupled, and is also comprised of a processor/cache bus interface for coupling to an external CPU. As disclosed, the cache memory management system can function as either an instruction cache with instruction prefetch capability, and on-chip program counter capabilities, and as a data cache memory management system which has an address register for receiving addresses from the CPU, to initiate a transfer of defined numbers of words of data commencing at the transmitted address.
Another novel feature disclosed is the quad-word boundary, quad-word line registers, and quad-word boundary detector subsystem, which accelerates access of data within quad-word boundaries, and provides for effective prefetch of sequentially ascending locations of storage instructions or data from the cache memory subsystem.
摘要翻译：公开了缓存和存储器管理系统体系结构和相关协议。高速缓存和存储器管理系统由组相联存储器高速缓存子系统，组相联转换逻辑存储器子系统，硬接线页面转换，可选择的存取模式逻辑以及有选择的可启动指令预取逻辑组成。高速缓存和存储器管理系统包括用于耦合到与主存储器耦合的系统总线的系统接口，并且还包括用于耦合到外部CPU的处理器/高速缓存总线接口。如所公开的，高速缓冲存储器管理系统可以用作具有指令预取能力的指令高速缓冲存储器和片上程序计数器能力，并且作为具有用于接收来自CPU的地址的地址寄存器的数据高速缓冲存储器管理系统来启动从发送地址开始传送定义数量的数据字。所公开的另一新颖特征是四字边界，四字线寄存器和四字边界检测器子系统，其加速四字边界内的数据访问，并提供对存储指令或数据的顺序上升位置的有效预取来自缓存存储器子系统。

47. 发明公开

EP0512007A4 CLUSTER ARCHITECTURE FOR A HIGHLY PARALLEL SCALAR/VECTOR MULTIPROCESSOR SYSTEM 失效
标题翻译：高分辨率/矢量多媒体系统的集群架构
公开(公告)号：EP0512007A4
公开(公告)日：1995-11-29
申请号：EP91902920
申请日：1990-12-27
申请人： SUPERCOMPUTER SYSTEMS LTD
发明人： CHEN STEVE S , SIMMONS FREDERICK J , SPIX GEORGE A , WILSON JIMMIE R , MILLER EDWARD C , ECKERT ROGER E , BEARD DOUGLAS R
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F13/18
CPC分类号： G06F9/30087 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092
摘要： A cluster architecture for a highly parallel multiprocessor computer processing system (40) is comprised of one or more clusters of tightly-coupled, high-speed processors (10) capable of both vector and scalar parallel processing that can symmetrically access shared resources (12) associated with the cluster, as well as the shared resources associated with other clusters.

48. 发明授权

EP0299526B1 Queue having long word length 失效
标题翻译：具有大的字长队列。
公开(公告)号：EP0299526B1
公开(公告)日：1995-04-19
申请号：EP88111432.6
申请日：1988-07-15
申请人： NEC CORPORATION
发明人： Nomura, Masahiro , Katori, Shigetatsu
IPC分类号： G06F5/06 , G06F9/38
CPC分类号： G06F5/10 , G06F9/3802 , G06F9/3814 , G06F2205/108

49. 发明公开

EP0525375A2 Microcomputer and divider circuit 失效
标题翻译： Mikrocomputer和Teilerschaltung。
公开(公告)号：EP0525375A2
公开(公告)日：1993-02-03
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.
摘要翻译： RISC型微处理器的固定结构长度为2 n位，数据使用大小为2 m，m大于或等于n。

50. 发明公开

EP0498067A2 Microcode generation for a scalable compound instruction set machine 失效
标题翻译： Mikrokodeerzeugungfüreine Maschine mit skalierbarem Verbundbefehlssatz。
公开(公告)号：EP0498067A2
公开(公告)日：1992-08-12
申请号：EP91121157.1
申请日：1991-12-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeremiah, Thomas L.
IPC分类号： G06F9/28
CPC分类号： G06F9/3814 , G06F9/28
摘要： An apparatus for generating microcode in a scalable compound instruction set machine operates in response to compounding information indicating that two or more adjacent instructions are to be executed in parallel. Separate and independent microcode is held in control store for each possible instruction in a group. Microcode sequences for each instruction of a group of instructions to be executed in parallel are merged in response to the compounding information into a single microinstruction sequence.
摘要翻译：用于在可伸缩复合指令集机器中生成微代码的装置响应于指示要并行执行两个或多个相邻指令的复合信息而进行操作。单独和独立的微码在控制存储器中保存在组中的每个可能的指令。要并行执行的一组指令的每个指令的微代码序列被合并以响应于复合信息到单个微指令序列中。

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