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41. 发明公开

EP0306644A2 Data processor having a break function 失效
标题翻译： Datenprozessor mit einer Unterbrechungsfunktion。
公开(公告)号：EP0306644A2
公开(公告)日：1989-03-15
申请号：EP88110176.0
申请日：1988-06-24
申请人： HITACHI, LTD.
发明人： Kurakazu Keiichi , Aoto, Yoshikazu , Baba, Shiro , Masuda, Satoshi , Kida, Hiroyuki , Kawashima, Shinji , Naruse, Yoshiaki
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally, is disposed, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.
摘要翻译：布置保存在存储器电路中的SWI指令的电路，以响应于外部提供的信号而被切换地输入，从而可以使用这样的内部电路来实现对程序字的替换，使得高速可靠休息可以实现。此外，通过设置指定的操作模式来建立与正常中断分离的中断功能，由此当数据处理器用作仿真器时，可以通过利用特殊中断功能容易地实现包括普通中断处理的用户程序的中断。此外，通过附加地提供表示中断状态的信号的功能，可以简化外部电路。

42. 发明公开

EP0220682A2 Data processing system 失效
标题翻译： Datenverarbeitungssystem。
公开(公告)号：EP0220682A2
公开(公告)日：1987-05-06
申请号：EP86114722.1
申请日：1986-10-23
申请人： HITACHI, LTD.
发明人： Baba, Shiro
IPC分类号： G06F9/30 , G06F9/46 , G06F9/34
CPC分类号： G06F9/30032 , G06F9/30098 , G06F9/3012 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/462 , G06F9/463
摘要： A data processing system has a data processing function to perform a data processing by specifying one of a plurality of register groups (BNO, BN1, BN2) according to an instruction. The instruction contains an information for indicating a change from a register group (BNO) to another register group (BN2) and an information for specifying desired one or two or more registers (R2, R15; R7, R12) in said register group(s). This enables to transfer the contents of the desired one or two or more registers to other registers at a register change.
摘要翻译：数据处理系统具有通过根据指令指定多个寄存器组（BN0，BN1，BN2）中的一个来执行数据处理的功能。指令包含用于指示从寄存器组（BN0）到另一寄存器组（BN2）的改变的信息和用于在所述寄存器组（BN2）中指定期望的一个或两个或更多个寄存器（R2，R15; R7，R12）的信息）。这使得能够在寄存器改变时将期望的一个或两个或多个寄存器的内容传送到其他寄存器。

43. 发明公开

EP1094470A1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：在快闪存储器和微处理器与快闪存储器共享存储器块中的数据线的无干扰
公开(公告)号：EP1094470A1
公开(公告)日：2001-04-25
申请号：EP00121759.5
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.
摘要翻译：一种半导体集成电路器件包括一个中央处理单元（CPU），一个第一外部端子（EA0-EA16），以及电可擦可编程非易失性快闪存储器（FMRY）worin的半导体集成电路具有第一操作模式，其中闪速存储器接收到来自中央处理单元中执行的控制程序，以从和到闪速存储器擦除和写入数据地址信号和worin的半导体集成电路具有在闪速存储器接收到的外部地址信号的第二操作模式终端写入从半导体集成电路装置的外部供给到所述闪存中的数据。

44. 发明授权

EP0364743B1 Development method of data processing system 失效
标题翻译：一个数据处理系统的设计过程
公开(公告)号：EP0364743B1
公开(公告)日：1997-05-28
申请号：EP89117257.9
申请日：1989-09-18
申请人： HITACHI, LTD.
发明人： Akao, Yasushi , Baba, Shiro , Sawase, Terumi , Hagiwara, Yoshimune
IPC分类号： G06F15/78 , G06F9/24
CPC分类号： G06F9/24 , G06F15/7814

45. 发明公开

EP0741358A2 Microcomputer 失效
标题翻译： Mikrorechner
公开(公告)号：EP0741358A2
公开(公告)日：1996-11-06
申请号：EP96302800.6
申请日：1996-04-22
申请人： HITACHI, LTD.
发明人： Ohsuga, Hiroshi , Kiuchi, Atsushi , Hasegawa, Hironobu , Baji, Toru , Noguchi, Koki , Akao, Yasushi , Baba, Shiro
IPC分类号： G06F15/78
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
摘要翻译：内置存储器分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。由此，CPU核心2可以同时从内置存储器传送两个数据值到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。

46. 发明授权

EP0306962B1 Single-chip microcomputer 失效
标题翻译：单片机。
公开(公告)号：EP0306962B1
公开(公告)日：1994-11-30
申请号：EP88114710.2
申请日：1988-09-08
申请人： HITACHI, LTD.
发明人： Sawase, Terumi , Noguchi, Kouki , Nakamura, Hideo , Akao, Yasushi , Baba, Shiro , Hagiwara, Yoshimune
IPC分类号： G06F9/24 , G06F15/78
CPC分类号： G06F9/24 , G06F15/7814

47. 发明公开

EP0306962A3 Single-chip microcomputer 失效
标题翻译：单芯片微型计算机
公开(公告)号：EP0306962A3
公开(公告)日：1990-04-11
申请号：EP88114710.2
申请日：1988-09-08
申请人： HITACHI, LTD.
发明人： Sawase, Terumi , Noguchi, Kouki , Nakamura, Hideo , Akao, Yasushi , Baba, Shiro , Hagiwara, Yoshimune
IPC分类号： G06F9/24 , G06F15/78
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit (6) built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby a logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.

48. 发明公开

EP0183231A3 Data processor 有权
标题翻译：数据处理器
公开(公告)号：EP0183231A3
公开(公告)日：1989-02-15
申请号：EP85115002.9
申请日：1985-11-26
申请人： HITACHI, LTD.
发明人： Baba, Shiro
IPC分类号： G06F12/06
CPC分类号： G06F12/0653
摘要： A microprocessor has a register (CR) in which attributive data corresponding to a memory to be coupled to the microprocessor is written, and a control circuit (DCD) which controls address signals to be supplied to the memory in accordance with the attributive data (B o , B i , B 2 ). The attributive data is composed of range data for discriminating ranges of address data supplied to an address bus, system data indicative of addressing systems of the memories corresponding to the respective address ranges, and bit number data indicative of numbers of address bits of the memories. Thus, in a case where the memory to be accessed is of an address multiplexing system as in a dynamic RAM, the address data of the address bus is divided into row address data and column address data, which are then supplied to the memory in time division.

49. 发明公开

EP0220684A2 Data processing system 失效
公开(公告)号：EP0220684A2
公开(公告)日：1987-05-06
申请号：EP86114724.7
申请日：1986-10-23
申请人： HITACHI, LTD.
发明人： Kurakazu, Keiichi , Baba, Shiro
IPC分类号： G06F9/34 , G06F9/30
CPC分类号： G06F9/30192
摘要： An instruction having two operands including a field (Sz2) specifying the bit length of a source operand and a field (Sz1) specifying the bit length of data to be operated by the execution unit. Based on size information stored in these fields (Sz1, Sz2), the operand bit length is modified, which unnecessitates the modification of the bit length of an operand by use of a macro instruction Consequently, the program execution speed can be improved.

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