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1. 发明授权

EP0893799B1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：与无干扰的数据线划分快闪存储器及微型电子计算机，以便存储块
公开(公告)号：EP0893799B1
公开(公告)日：2002-12-04
申请号：EP98118740.4
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

2. 发明公开

EP0658904A3 Semiconductor integrated circuit device 失效
标题翻译：的半导体集成电路。
公开(公告)号：EP0658904A3
公开(公告)日：1996-06-05
申请号：EP94118793.2
申请日：1994-11-29
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORP.
发明人： Kubono, Shooji , Kume, Hitoshi
IPC分类号： G11C16/06 , G11C5/14 , G05F3/24
CPC分类号： G11C16/30 , G11C5/145 , G11C5/147 , G11C16/10
摘要： A semiconductor integrated circuit comprising a charge pump circuit for forming a step-up (boost) voltage higher than a desired internal voltage, a voltage dividing circuit which forms a plurality of divided voltages based on a reference voltage, and control circuit which intermittently is operated the charge pump circuit so that an output voltage of the charge pump circuit provides the desired internal voltage obtained by adding a voltage obtained by multiplying a particular voltage among the plurality of divided voltages by n to a predetermined divided voltage.

3. 发明授权

EP1094470B1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：在快闪存储器和微处理器与快闪存储器共享存储器块中的数据线的无干扰
公开(公告)号：EP1094470B1
公开(公告)日：2003-08-13
申请号：EP00121759.5
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

4. 发明公开

EP0790559A1 Method of monitoring a computer system, featuring performance data distribution to plural monitoring processes 失效
标题翻译： Verfahren zurÜberwachungeines Computersystems mit Leistungsdatenverteilung an mehrereÜberwachungsprozesse
公开(公告)号：EP0790559A1
公开(公告)日：1997-08-20
申请号：EP97102343.7
申请日：1997-02-13
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORP.
发明人： Takubo, Shunji , Sagawa, Nobutoshi , Ohta, Tadashi , Yamaga, Susumu
IPC分类号： G06F11/34
CPC分类号： G06F11/32 , G06F11/3404 , G06F11/3495
摘要： In order to enable monitoring of a computer of a monitoring target, by two or more computers by way of a network, without increasing the load of the computer of monitoring target, the capturing process (4) invoked on each node (2) of the parallel computer (1) captures performance data, the collecting process (3) invoked on a specific node collects these captured performance data, and transmits to the relaying process (15) on the monitoring computer (11). If there is a display process (16) and a logging process (17) invoked on the same or different monitoring computers (11), the relaying process (15) distributes the performance data to them. The display process (16) displays the performance data for part of measurement items included in the distributed performance data on the display device (12). The logging process (17) stores all the distributed performance data in the storage device (13).
摘要翻译：为了能够通过两个或多个计算机通过网络来监视监视目标的计算机，而不增加监视目标的计算机的负载，在每个节点（2）上调用的捕获进程（4）并行计算机（1）捕获性能数据，在特定节点上调用的收集处理（3）收集这些捕获的性能数据，并将其发送到监视计算机（11）上的中继处理（15）。如果在相同或不同的监控计算机（11）上调用了显示过程（16）和记录过程（17），则中继处理（15）将演奏数据分发给它们。显示处理（16）在显示装置（12）上显示包含在分布式演奏数据中的部分测量项目的演奏数据。记录过程（17）将所有分布式演示数据存储在存储装置（13）中。

5. 发明公开

EP0658904A2 Semiconductor integrated circuit device 失效
标题翻译： Integrierte Halbleiterschaltungsanordnung。
公开(公告)号：EP0658904A2
公开(公告)日：1995-06-21
申请号：EP94118793.2
申请日：1994-11-29
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORP.
发明人： Kubono, Shooji , Kume, Hitoshi
IPC分类号： G11C16/06 , G11C5/14 , G05F3/24
CPC分类号： G11C16/30 , G11C5/145 , G11C5/147 , G11C16/10
摘要： A semiconductor integrated circuit comprising a charge pump circuit for forming a step-up (boost) voltage higher than a desired internal voltage, a voltage dividing circuit which forms a plurality of divided voltages based on a reference voltage, and control circuit which intermittently is operated the charge pump circuit so that an output voltage of the charge pump circuit provides the desired internal voltage obtained by adding a voltage obtained by multiplying a particular voltage among the plurality of divided voltages by n to a predetermined divided voltage.
摘要翻译：一种半导体集成电路，包括用于形成高于期望内部电压的升压（升压）电压的电荷泵电路，基于参考电压形成多个分压的分压电路和间歇地操作的控制电路电荷泵电路，使得电荷泵电路的输出电压提供通过将通过将多个分压之间的特定电压乘以n而获得的电压加到预定分压而获得的期望内部电压。

6. 发明公开

EP1094470A1 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：在快闪存储器和微处理器与快闪存储器共享存储器块中的数据线的无干扰
公开(公告)号：EP1094470A1
公开(公告)日：2001-04-25
申请号：EP00121759.5
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.
摘要翻译：一种半导体集成电路器件包括一个中央处理单元（CPU），一个第一外部端子（EA0-EA16），以及电可擦可编程非易失性快闪存储器（FMRY）worin的半导体集成电路具有第一操作模式，其中闪速存储器接收到来自中央处理单元中执行的控制程序，以从和到闪速存储器擦除和写入数据地址信号和worin的半导体集成电路具有在闪速存储器接收到的外部地址信号的第二操作模式终端写入从半导体集成电路装置的外部供给到所述闪存中的数据。

7. 发明公开

EP0817276A1 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR 失效
标题翻译： HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN
公开(公告)号：EP0817276A1
公开(公告)日：1998-01-07
申请号：EP95912464.5
申请日：1995-03-17
申请人： HITACHI, LTD. , Hitachi, Ulsi Engineering Corp.
发明人： HIRATA, Koji Puchihaitsu Jousui Room 203 , TANOUE, Tomonori , MASUDA, Hiroshi , UCHIYAMA, Hiroyuki , MOCHIZUKI, Kazuhiro Hitachi Oowada Apato Room D302
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L23/481 , H01L27/0605 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large.
In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof is formed a through hole for contact of a size permitting exposure of at least part of a first conductor layer and a dielectric Si alloy layer present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer.
Since the semiconductor layer can be subjected to a selective dry etching for the dielectric Si alloy layer, the dielectric Si alloy layer is not etched at the time of forming the above through hole in the semiconductor layer, whereby an electric short-circuit of the second conductor layer with a single crystal semiconductor layer which underlies the dielectric Si alloy layer can be prevented.
摘要翻译：本发明涉及不仅具有异质结双极晶体管或异质绝缘栅场效应晶体管的半导体器件的接触结构，而且还涉及用于半导体器件的半导体器件。在多晶或非晶未掺杂的III-V族化合物半导体的半导体层或其合金中，形成有用于接触的通孔，其允许暴露于第一导体层的至少一部分和存在于第一导体层导体层，并且在通孔内形成第二导体层以与第一导体层接触。由于可以对半导体层进行用于电介质Si合金层的选择性干蚀刻，所以在形成半导体层中的上述通孔时不会蚀刻电介质Si合金层，从而使第二可以防止具有位于电介质Si合金层下面的单晶半导体层的导体层。

9. 发明授权

EP0902436B1 Microcomputer with flash memory programmable via external terminal 失效
标题翻译：微机与外部连接端子可编程闪存
公开(公告)号：EP0902436B1
公开(公告)日：2002-10-16
申请号：EP98118739.6
申请日：1993-03-11
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORP.
发明人： Matsubara, Kiyoshi , Yashiki, Naoki , Baba, Shiro , Ito, Takashi , Mukai, Hirofumi , Sato, Masanao , Terasawa, Masaaki , Kuroda, Kenichi , Shiba, Kazuyoshi
IPC分类号： G11C16/06 , G06F9/445
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor integrated circuit device comprises a central processing unit (CPU), a first external terminal (EA0-EA16), and an electrically erasable and programmable nonvolatile flash memory (FMRY), wherein the semiconductor integrated circuit has a first operation mode in which the flash memory receives an address signal from the central processing unit executing a control program to erase and write data from and into the flash memory, and wherein the semiconductor integrated circuit has a second operation mode in which the flash memory receives an address signal on the external terminal to write data supplied from the outside of the semiconductor integrated circuit device into the flash memory.

10. 发明公开

EP0619541A3 Flash memory control method and information processing system therewith 失效
标题翻译： Flash-Speichersteuerverfahren und Informationsverarbeitungssystemdafür。
公开(公告)号：EP0619541A3
公开(公告)日：1995-03-01
申请号：EP94105467.8
申请日：1994-04-08
申请人： HITACHI, LTD. , HITACHI KEIYO ENGINEERING CO., LTD. , HITACHI ULSI ENGINEERING CORP.
发明人： Tobita, Tsunehiro , Kitahara, Jun , Tsunehiro, Takashi , Katayama, Kunihiro , Hattori, Ryuichi , Seki, Yukihiro , Yamagami, Hajime , Totsuka, Takashi , Wada, Takeshi , Takaya, Yosio , Saito, Manabu , Kaki, Kenichi , Okubo, Takao , Kikuchi, Takashi , Kishi, Masamichi , Suzuki, Takeshi , Kadowaki, Shigeru
IPC分类号： G06F3/06 , G06F12/08 , G06F11/20 , G11C16/06
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.
摘要翻译：当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器以及控制控制器的控制部分，其中对应于由访问一个外部系统。第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。控制器包括控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，存储确定的物理扇区地址的装置，以及用于连续生成由物理扇区地址确定的扇区中的地址的装置。控制部分响应于接口信息，第一管理信息和用于控制/从外部系统输入/输出数据的第二管理信息，并且用于从外部系统将写数据临时存储到第一非易失性存储器中然后将写入数据从易失性存储器传送到第一非易失性存储器。当从第一非易失性存储器输出物理扇区地址的数据时，连续的地址产生装置和扇区地址存储装置将物理扇区地址和连续生成的地址输出到第一非易失性存储器和易失性存储器，扇区地址被输入到易失性存储器。

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