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31. 发明公开

EP1315328A2 Multi-phase sampling 有权
标题翻译：多相采样
公开(公告)号：EP1315328A2
公开(公告)日：2003-05-28
申请号：EP02021683.4
申请日：2002-09-27
申请人： Agilent Technologies, Inc.
发明人： Walker, Richard C.
IPC分类号： H04L7/033 , H03L7/089 , H03D13/00
CPC分类号： H04L7/033 , H03L7/081 , H03L7/091 , H03L7/0995 , H04L7/0004 , H04L7/0037
摘要： The present invention provides a multi-phase sampling system (3, 10) in which each sampler (4, 5, 6, 11, 12, 13) samples a transition and data of an incoming data signal (2, 14). By enabling each sampler to sample a transition in addition to data of the incoming data signal, phase errors associated with each of the samplers can be determined (30). The phase error determinations (24, 25, 26) provide valuable information that can be used 1) to correct the phase errors of the system sampling the incoming data signal, 2) to correct the phase errors of a multi-phase system that is transmitting the incoming data signal, and/or 3) to correct the phase errors of both a multi-phase system that is sampling an incoming data signal and of a multi-phase system that is transmitting the data signal.

32. 发明公开

EP1178609A3 Phase detector 有权
公开(公告)号：EP1178609A3
公开(公告)日：2002-10-16
申请号：EP01000263.2
申请日：2001-07-02
申请人： Texas Instruments Inc.
发明人： Staszewski, Robert , Leipold, Dirk
IPC分类号： H03D13/00 , H03L7/091 , H03L7/085
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector (200) is provided to realize a frequency synthesizer architecture (100) that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO (104) and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector (200) is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock (110) and a reference clock by using a time-to-digital converter (201) to express the time difference as a digital word for use by the frequency synthesizer.

33. 发明公开

EP1232564A1 POWER AMPLIFIERS 审中-公开
标题翻译：功率放大器
公开(公告)号：EP1232564A1
公开(公告)日：2002-08-21
申请号：EP00971429.6
申请日：2000-11-06
申请人： TELEFONAKTIEBOLAGET LM ERICSSON
发明人： BRANDT, Per-Olof
IPC分类号： H03D13/00 , H03D1/10 , H03F1/32 , H03G3/30
CPC分类号： H03F1/3282
摘要： A circuit for controlling the characteristics of a power amplifier comprises first and second inputs (2, 4), a first amplitude detection circuit (8, 10, 12, 16) having an input and an output (14), the input being connected to the first input, and the first detection circuit being operable to produce a first output signal indicative of the amplitude of an input signal received at its input, a second amplitude detection circuit (20, 22, 24, 28) having an input and output (26), the input being connected to the second input, and the second detection circuit being operable to produce a second output signal indicative of the amplitude of an input signal received at its input. The circuit also includes a phase detection circuit (34) having an input and an output (36), the input being connected to each of the first and second inputs, and being operable to produce a phase signal indicative of the relative phase between input signal supplied to the first and second inputs, an amplitude control circuit (40, 42) connected to receive the outputs of the first and second amplitude detection circuits and operable to produce an amplitude control signal therefrom, and a phase control circuit (44, 46) connected to receive the output of the phase detection circuit and operable to produce a phase control signal therefrom.
摘要翻译：用于控制功率放大器的特性的电路包括第一和第二输入端（2,4），具有输入端和输出端（14）的第一幅度检测电路（8,10,12,16），所述输入端连接到所述第一输入端和所述第一检测电路可操作以产生指示在其输入端处接收的输入信号的幅度的第一输出信号;第二幅度检测电路（20,22,24,28），其具有输入端和输出端（所述输入连接到所述第二输入，并且所述第二检测电路可操作以产生指示在其输入处接收的输入信号的幅度的第二输出信号。该电路还包括具有输入端和输出端（36）的相位检测电路（34），输入端连接到第一和第二输入端中的每一个，并且可操作以产生指示输入信号提供给第一和第二输入端;幅度控制电路（40,42），被连接以接收第一和第二幅度检测电路的输出并可操作以从其中产生幅度控制信号;以及相位控制电路（44,46）被连接以接收相位检测电路的输出并可操作以从其产生相位控制信号。

34. 发明公开

EP0991193A1 Appareil radioélectrique comportant un synthétiseur de fréquence et discriminateur de phase pour un tel appareil 审中-公开
标题翻译：无线电与频率合成器和鉴相器用于这种设备
公开(公告)号：EP0991193A1
公开(公告)日：2000-04-05
申请号：EP99203093.2
申请日：1999-09-21
申请人： Koninklijke Philips Electronics N.V.
发明人： Chabas, Jean Alain
IPC分类号： H03L7/089 , H03D13/00
CPC分类号： H03L7/0891 , H03D13/004
摘要： L'appareil de l'invention est muni d'un synthétiseur de fréquences (30) du type à verrouillage de phase. Pour obtenir un verrouillage rapide, on a disposé un discriminateur de phase (40) présentant une caractéristique optimale. Quand il n'y a pas de verrouillage de phase, sa tension de sortie reste constante, ce qui donne un gain important à la boucle pour obtenir la capture. Lorsqu'il y a verrouillage, le discriminateur donne une erreur proportionnelle à l'écart de phase. Le discriminateur de phase (40) comprend des premier et second circuits séquentiels, le premier circuit séquentiel (51,52,55) fournissant des signaux représentatifs de l'écart de phase alors que le deuxième circuit séquentiel (61,62) fournit un signal constant lorsqu'une différence de fréquence est détectée. Le premier circuit séquentiel (51,52,55) comprend avantageusement deux bascules de type D et le deuxième circuit séquentiel (61,62) peut comprendre deux bascules de type JK.
Application aux radiotéléphones.
摘要翻译：该频率合成器锁定装置具有鉴相器，比较输入和产生的信号，以锁定到输入信号。对于几乎两个运算电路按顺序运行，第一（51,52）来找到相分离和提供一次信号检测已经发生一个恒定频率信号的第二电路（61,62）。

35. 发明授权

EP0792011B1 A digital phase detector 失效
标题翻译：数字相位检测器
公开(公告)号：EP0792011B1
公开(公告)日：2000-01-05
申请号：EP96117625.2
申请日：1996-11-04
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Sommer, Jeremy S.
IPC分类号： H03D13/00 , H04L7/033
CPC分类号： H04L7/0331 , H03D13/001

36. 发明授权

EP0647017B1 Synchronization circuit using a high speed digital slip counter 失效
标题翻译：同步电路，快速数字转差频率计数器
公开(公告)号：EP0647017B1
公开(公告)日：1998-06-10
申请号：EP94306924.5
申请日：1994-09-21
申请人： AT&T Corp.
发明人： Bortolini, James Robert
IPC分类号： H03D13/00 , G01R23/00
CPC分类号： H03L7/085 , G01R23/005 , H03D13/001

37. 发明授权

EP0331016B1 Phase detector circuit for periodic signal using three sampling data 失效
标题翻译：为周期性信号，其使用三个样本相位检测器电路
公开(公告)号：EP0331016B1
公开(公告)日：1998-05-27
申请号：EP89103194.0
申请日：1989-02-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA AVE CO., LTD
发明人： Enomoto, Akihiko c/o Patent Division , Koga, Takashi c/o Patent Division , Yoneda, Minoru c/o Patent Division , Kobata, Hiroshi c/o Patent Division
IPC分类号： H03D13/00 , H04N9/89 , H03L7/08
CPC分类号： H03L7/0812 , H03D13/00 , H03L7/091 , H04L7/0334 , H04N9/896

38. 发明公开

EP0792011A3 A digital phase detector 失效
标题翻译：数字相位检测器
公开(公告)号：EP0792011A3
公开(公告)日：1998-05-13
申请号：EP96117625
申请日：1996-11-04
申请人： HEWLETT PACKARD CO
发明人： CHU DAVID C , SOMMER JEREMY S
IPC分类号： G01R25/00 , H03D13/00 , H03L7/085 , H04L7/033
CPC分类号： H04L7/0331 , H03D13/001
摘要： In the present embodiment, digital phase detection of digital telecommunications signals is based on heterodyning. The frequency of two signals are scaled to different nominal values that are separated by a typically small but finite difference. The two frequencies are then mixed to generate a finite beat frequency. In mixing, phase is preserved and the finite beat frequency phase is in one-to-one correspondence with the signal phase. Phase detection is performed indirectly at the lower finite beat frequency with high resolution and greater ease than direct phase detection.

39. 发明授权

EP0749646B1 A PHASE ERROR PROCESSOR CIRCUIT WITH A COMPARATOR INPUT SWAPPING TECHNIQUE 失效
标题翻译：随着技术的比较器输入的交换相位误差处理器电路
公开(公告)号：EP0749646B1
公开(公告)日：1998-02-11
申请号：EP95944217.9
申请日：1995-12-20
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： WONG, Hee , LI, Gabriel, M.
IPC分类号： H03L7/085 , H03D13/00
CPC分类号： H03L7/085 , H03L7/0991 , H04L7/0083 , H04L7/033
摘要： A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs off a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams. The output of the exclusive-OR gate is coupled to the input of a D flip flop which is latched once per window. The output of the D flip flop is an UP/ DOWN signal which controls an oscillator, which generates the local clock signal, to advance or retard the phase of the local clock in response to the condition of the UP/ DOWN signal.

40. 发明授权

EP0585806B1 Digitaler Phasenkomparator und Phasenregelkreis 失效
标题翻译：数字相位比较器和锁相环
公开(公告)号：EP0585806B1
公开(公告)日：1997-07-23
申请号：EP93113625.3
申请日：1993-08-26
申请人： Alcatel SEL Aktiengesellschaft
发明人： Rieder, Klaus-Hartwig
IPC分类号： H03L7/085 , G01R25/08 , H03D13/00
CPC分类号： G01R25/08 , H03D13/001 , H03L7/089

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