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1. 发明授权

EP0547292B1 Picosecond event timer 失效
标题翻译：钟表在皮秒事件
公开(公告)号：EP0547292B1
公开(公告)日：1996-01-17
申请号：EP92113443.3
申请日：1992-08-06
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Knotts, Thomas A.
IPC分类号： G04F10/00
CPC分类号： G01R29/0273

2. 发明公开

EP0792011A2 A digital phase detector 失效
标题翻译：数码相机Phasendetektor
公开(公告)号：EP0792011A2
公开(公告)日：1997-08-27
申请号：EP96117625.2
申请日：1996-11-04
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Sommer, Jeremy S.
IPC分类号： H03D13/00 , H04L7/033
CPC分类号： H04L7/0331 , H03D13/001
摘要： In the present embodiment, digital phase detection of digital telecommunications signals is based on heterodyning. The frequency of two signals are scaled to different nominal values that are separated by a typically small but finite difference. The two frequencies are then mixed to generate a finite beat frequency. In mixing, phase is preserved and the finite beat frequency phase is in one-to-one correspondence with the signal phase. Phase detection is performed indirectly at the lower finite beat frequency with high resolution and greater ease than direct phase detection.
摘要翻译：在本实施例中，数字电信信号的数字相位检测基于外差。两个信号的频率被缩放到不同的标称值，这些标称值被典型的小但有限的差分开。然后混合两个频率以产生有限的拍频。在混合中，保留相位，有限拍频相位与信号相位一一对应。相位检测以较低的有限拍频间接执行，分辨率高，易于直接相位检测。

3. 发明公开

EP0547292A1 Picosecond event timer 失效
标题翻译： ZeitmesserfürEreignisse im Picosekundenbereich。
公开(公告)号：EP0547292A1
公开(公告)日：1993-06-23
申请号：EP92113443.3
申请日：1992-08-06
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Knotts, Thomas A.
IPC分类号： G04F10/00 , G04F10/04
CPC分类号： G01R29/0273
摘要： A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer (15) is a circuit section which subdivides a period from a phase-locked ring-oscillator (13) into 2N subparts (39). An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code (41) which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator (13) by the use of linear combiner elements (71, 73, 75). The dual thermometer code (41), encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event (11) also latches the count states of a pair of lead-lag counters (150, 151) in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs. Only one reading is chosen for recording as determined by the most significant bit of the fine code. The choice will always find an accurate and stable reading, and reject erroneous readings resulting from reading a counter in transition. The chosen counter reading, encoded to binary, forms the coarse timer (17) for the binary word representation of the event time. The coarse and fine binary words are butt-joinable to form the complete binary timing representation without further arithmetic processing.
摘要翻译：用于时间戳事件信号的电路，例如。过零点，使用粗细和定时器。精细定时器（15）是将锁相环形振荡器（13）的周期分为2N个子部分（39）的电路部分。通过锁定特定子部件的数字表示来定时事件信号。子部件的数字表示是N位双温度计代码（41），其唯一地标识每个子部分，其中每个相邻子部分仅差一位。通过使用线性组合器元件（71,73,75），子部件在时间量化中比在环形振荡器（13）中的一个有源元件的传播延迟更精细。编码后锁定成二进制码的双温度计代码（41）形成事件时间的二进制字表示的“精细”定时部分。事件（11）还在主从配置计数环形振荡器周期中锁存一对超前滞后计数器（150,151）的计数状态。这些计数器在双温度计代码转换之前和之后分别改变状态。只有一个读取被选择用于记录，由精细代码的最高有效位确定。选择将始终找到准确稳定的阅读，并拒绝在转换期间读取计数器导致的错误读数。编码为二进制的所选计数器读数形成事件时间的二进制字表示的粗定时器（17）。粗略和精细的二进制字是对接的，以形成完整的二进制定时表示，而无需进一步的算术处理。

4. 发明公开

EP0792037A1 Feed forward generation of a clock signal 失效
标题翻译： “前进”Erzeugung eines Taktsignals
公开(公告)号：EP0792037A1
公开(公告)日：1997-08-27
申请号：EP96118127.8
申请日：1996-11-12
申请人： Hewlett-Packard Company
发明人： Chu, David C.
IPC分类号： H04J3/06 , H04L7/00 , H03L7/00
CPC分类号： H04J3/0688 , H04L7/0083
摘要： In the present invention, a feed forward apparatus (2) and method discipline a clock signal (11) by a reference signal (R) in digital telecommunication networks. In a first embodiment of the present invention, a synthesizer correction term (ds) comprises a frequency correction term (df). In the event that one frequency correction term (df1) is selected in place of another frequency correction term (df2) the phase of the clock signal (11) remains free from extraneous frequency or phase variations during the transition. In a second embodiment of the present invention, the synthesizer correction term comprises a phase correction term (dp). Complete phase coherence between the reference signal and the clock signal results.
Multiple scaled phase detectors (PD) may also be used to generate multiple synthesizer correction terms (ds) from different references (REF1,REF2). Selection of one of the synthesizer correction terms (ds) disciplines the clock signal (11) by that reference signal (R) corresponding to the selected synthesizer correction term (ds).
摘要翻译：在本发明中，前馈装置（2）和方法通过数字电信网络中的参考信号（R）来纪录时钟信号（11）。在本发明的第一实施例中，合成器校正项（ds）包括频率校正项（df）。在选择一个频率校正项（df1）代替另一个频率校正项（df2）的情况下，时钟信号（11）的相位在转换期间保持不受外来频率或相位变化的影响。在本发明的第二实施例中，合成器校正项包括相位校正项（dp）。参考信号与时钟信号之间的完全相位相干结果。多比例相位检测器（PD）也可用于从不同参考（REF1，REF2）产生多个合成器校正项（ds）。合成器校正项（ds）之一的选择通过与选择的合成器校正项（ds）相对应的参考信号（R）对时钟信号（11）进行管理。

5. 发明授权

EP0792011B1 A digital phase detector 失效
标题翻译：数字相位检测器
公开(公告)号：EP0792011B1
公开(公告)日：2000-01-05
申请号：EP96117625.2
申请日：1996-11-04
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Sommer, Jeremy S.
IPC分类号： H03D13/00 , H04L7/033
CPC分类号： H04L7/0331 , H03D13/001

6. 发明公开

EP0792022A1 Phase-locked digital synthesizers 失效
标题翻译：在锁相环数字频率合成器
公开(公告)号：EP0792022A1
公开(公告)日：1997-08-27
申请号：EP96117426.5
申请日：1996-10-30
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Sommer, Jeremy S.
IPC分类号： H03L7/07 , G06F11/16 , G06F1/12
CPC分类号： H04L1/22 , H03L7/07 , H04L7/0083
摘要： A method of phase-locking one digital frequency synthesizer to another, the former frequency synthesizer thereby being slaved to the latter, which may be called the master. When the outputs of said frequency synthesizers are both made available to downstream circuitry, such that the one which is master is always selected, this phase-locking minimizes the phase hits which occur as a result of switching the master to be slave and vice-versa. The method provides for this switching (known as rearrangement) to be done automatically and rapidly in the event of failure of the master frequency synthesizer.

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