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31. 发明授权

EP0792514B1 METHOD OF MAKING AN INTEGRATED CIRCUIT WITH COMPLEMENTARY ISOLATED BIPOLAR TRANSITORS 失效
标题翻译：具有隔离互补双极晶体管过程中的集成电路
公开(公告)号：EP0792514B1
公开(公告)日：2005-03-23
申请号：EP95940602.6
申请日：1995-11-02
申请人： ANALOG DEVICES, INCORPORATED
发明人： LAPHAM, Jerome, F. , SCHARF, Brad, W.
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L21/761 , H01L21/82285 , H01L27/0826 , H01L29/7322
摘要： Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well (11) is formed in a P-type substrate (10). P-type dopant is implanted in the N-well (11) to become a sub-collector (12) for a pnp transistor. N-type dopant is implanted in the substrate (10) in a location laterally displaced from the N-well (11) to become a sub-collector (18) for an npn transistor. N-type material is implanted in the N-well (11) to begin the formation of an isolation wall (16) for the pnp transistor. A P-type epitaxial (epi) layer (20) then is grown over the P-type substrate (10). N-type material is implanted in the epi layer (20) to complete the isolation wall (22) for the pnp transistor, and to complete the collector (24) for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer (20) to form the bases (30, 34) and emitters (32, 40) for the npn and pnp transistors.

32. 发明公开

EP1225626A3 Semiconductor integrated circuit device and manufacture method therefor 有权
标题翻译：一种半导体集成电路，及其制造方法
公开(公告)号：EP1225626A3
公开(公告)日：2005-01-12
申请号：EP02250304.9
申请日：2002-01-16
申请人： FUJI ELECTRIC CO., LTD.
发明人： Kitamura, Akio
IPC分类号： H01L21/8234
CPC分类号： H01L21/8249 , H01L21/761 , H01L21/823412 , H01L21/823456 , H01L21/823493 , H01L27/0635
摘要： The object of the present invention is to mount a submicron CMOS transistor on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate 1, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area 4 is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

33. 发明公开

EP1213760A3 Selective substrate implant process for decoupling analog and digital grounds 有权
标题翻译：在衬底中选择性Implantierverfahren用于模拟和数字地面的去耦
公开(公告)号：EP1213760A3
公开(公告)日：2004-03-31
申请号：EP01128845.3
申请日：2001-12-04
申请人： MICREL INCORPORATED
发明人： McCormack, Stephen , Alter, Martin , Wrathall, Robert S. , Laber, Carlos Albertos
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/761
CPC分类号： H01L27/092 , H01L21/761 , H01L21/823878 , H01L21/823892
摘要： An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

34. 发明公开

EP1367717A1 Semiconductor switch including isolated MOS-transistors 有权
标题翻译： Halbleiterschalter mit isolierten MOS-Transistoren
公开(公告)号：EP1367717A1
公开(公告)日：2003-12-03
申请号：EP03090167.2
申请日：2003-05-30
申请人： NEC Compound Semiconductor Devices, Ltd.
发明人： Okashita, Tomonori, c/o NEC Compound
IPC分类号： H03K17/693
CPC分类号： H01L27/088 , H01L21/761 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/823481 , H01L27/1203 , H03K17/6871 , H03K17/693
摘要： In a semiconductor switch apparatus including an input terminal (IN), an output terminal (OUT1), an AC ground terminal (AC-GND), a DC ground terminal (DC-GND), at least one series MOS transistor (1, 1') connected between the input terminal and the output terminal, and at least one shunt MOS transistor (2, 2') connected between one of the input terminal and the output terminal and the AC ground terminal, the series MOS transistor is formed within a first region of a semiconductor layer on a silicon-on-insulator configuration surrounded by a first trench insulating layer (T1), and the shunt MOS transistor is formed within a second region of the semiconductor layer surrounded by a second trench insulating layer (T2).
摘要翻译：在包括输入端子（IN），输出端子（OUT1），AC接地端子（AC-GND），DC接地端子（DC-GND），至少一个串联MOS晶体管（1,1） '）连接在输入端子和输出端子之间，以及至少一个分流MOS晶体管（2,2'），其连接在输入端子和输出端子之一和AC接地端子之间，串联MOS晶体管形成在由第一沟槽绝缘层（T1）包围的绝缘体上硅结构上的半导体层的第一区域，并且分流MOS晶体管形成在由第二沟槽绝缘层（T2）包围的半导体层的第二区域内，。

35. 发明公开

EP1130638A3 Method and structure for reducing leakage currents of active area diodes and source/drain diffusions 有权
标题翻译：一种用于降低二极管的和掺杂源的有效区域的漏电流的方法和结构/漏区
公开(公告)号：EP1130638A3
公开(公告)日：2003-10-15
申请号：EP01300708.3
申请日：2001-01-26
申请人： Agilent Technologies, Inc. (a Delaware corporation)
发明人： Kopley, Thomas Edward , Vook, Dietrich W. , Dungan, Thomas
IPC分类号： H01L21/762 , H01L27/146
CPC分类号： H01L21/761 , H01L27/14603 , H01L27/14609 , H01L27/14689
摘要： A fabrication method for providing isolation between adjacent regions of an integrated circuit (10) includes providing a guard layer (40; 68; 72; 88; 90; and 128) over field edges that are the interfaces between field oxide regions (30; 54; and 92) and diffusion regions (14; 26; 52; 86; and 96) in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip (42; 70; and 130) is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.
摘要翻译：用于集成电路的相邻区域之间提供隔离的制造方法（10），包括提供一个保护层（40; 68; 72; 88; 90; 128）在字段边缘确实是场氧化区（30之间的界面; 54 ;和92）和扩散区域（14; 26; 52; 86;在这种掺杂剂和96）被引入。该保护层会抑制引入沿着场边缘的掺杂剂，所以没有一个基本上不含掺杂剂的过渡条带（42; 70;和130）形成。过渡条抑制从有源区至场氧化区的漏电流。在一个实施例中，有源区是一有源区二极管，颜色：例如用于形成在有源像素传感器（APS）的像素。该保护层被施力，从而つweiterer电路操作期间抑制电流泄漏。在另一个实施方案中，方法是在用于具有以覆盖光电二极管结构APS像素的晶体管的制造中使用。

36. 发明公开

EP1335425A1 SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD 审中-公开
标题翻译： HALBLEITERBAUEMENT在SEIN PRODUKTIONSVERFAHREN
公开(公告)号：EP1335425A1
公开(公告)日：2003-08-13
申请号：EP01976761.5
申请日：2001-10-19
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , SHIBATA, Akihide , KAKIMOTO, Seizo
IPC分类号： H01L21/8234 , H01L27/08 , H01L29/78 , H01L21/336 , H01L21/76 , H01L21/761
CPC分类号： H01L21/823481 , H01L21/761 , H01L21/76202 , H01L21/76232 , H01L21/823493
摘要： A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).
摘要翻译：一种半导体器件，其具有在阱区的边界处所需的两层阱结构和小的边界，并且包括衬底偏置可变晶体管和DTMOS。场效应晶体管（223）形成在P型浅阱区（212）上。 P型浅井区域（212）上的浅装置隔离区域（214）的深度小于N型深井区域（227）和P型浅井区域（ 212）。因此，场效应晶体管（223）共享P型浅阱区（212）。彼此独立的P型浅阱区域（212）由于它们通过深度器件隔离区域（226）和N型深阱区域（227）彼此隔离而容易地形成。

37. 发明公开

EP1291918A2 Integrated radio frequency circuits 有权
标题翻译：集成射频电路
公开(公告)号：EP1291918A2
公开(公告)日：2003-03-12
申请号：EP02255215.2
申请日：2002-07-26
申请人： Programmable Silicon Solutions
发明人： Wong, Ting-Wah , Woo, Chong L.
IPC分类号： H01L27/06 , H01L21/761
CPC分类号： H01L23/5227 , H01L21/761 , H01L21/823481 , H01L27/08 , H01L27/088 , H01L27/0928 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An RF circuit (310) may be formed over a triple well (316, 318, 320) that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits (310) to the substrate (316), improving the self-resonance frequency of inductors and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices, such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.
摘要翻译： RF电路（310）可以形成在产生两个反向偏置结的三重阱（316,318,320）之上。通过调节跨接点的偏置，可以减小跨接点的电容，减少从RF电路（310）到衬底（316）的电容耦合，改善电感器的自谐振频率并减少不需要的信号的耦合以及来自底层衬底的噪声，以及有源电路和无源组件（如电容和电感）。结果，诸如无线电，蜂窝电话和诸如蓝牙收发器，逻辑器件以及闪存和SRAM存储器设备之类的收发器的射频设备都可以使用CMOS制造工艺形成在相同的集成电路管芯中。

38. 发明公开

EP1287554A2 SHIELDING OF ANALOG CIRCUITS ON SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译： ABSCHRMUNG模拟电路在半导体衬底
公开(公告)号：EP1287554A2
公开(公告)日：2003-03-05
申请号：EP01946084.9
申请日：2001-06-05
申请人： Infineon Technologies North America Corp.
发明人： PRIGGE, Odin
IPC分类号： H01L21/761
CPC分类号： H01L21/761 , H01L21/76224
摘要： A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.

39. 发明公开

EP1203401A1 INTEGRATED INDUCTIVE CIRCUITS 审中-公开
标题翻译：集成电感电路
公开(公告)号：EP1203401A1
公开(公告)日：2002-05-08
申请号：EP00967395.5
申请日：2000-08-16
申请人： Programmable Silicon Solutions
发明人： WONG, Ting-wah
IPC分类号： H01L21/02 , H01L27/092 , H01L27/08
CPC分类号： H01L28/10 , H01L21/761 , H01L21/823481 , H01L23/5227 , H01L27/08 , H01L27/0928 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An RF circuit (12) may be formed over a triple well that creates two reverse biased junctions (66b and 66c). By adjusting the bias across the junctions, the capacitance (67a and 67b) across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate (42), improving the self-resonance frequency of inductors (48, 50) and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices (10), such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.

40. 发明公开

EP1193752A1 Method to form a localized silicon-on-insulator structure 审中-公开
标题翻译： Verfahren zur Herstellung einer lokalisierten Silizium-auf-Isolator-Struktur
公开(公告)号：EP1193752A1
公开(公告)日：2002-04-03
申请号：EP00402680.3
申请日：2000-09-28
申请人： MOTOROLA, INC.
发明人： Roux, Sylvie , Dilhac, Jean-Marie , Bafleur, Maryse , Charitat, Georges , Pages, Irenée
IPC分类号： H01L21/762 , H01L21/20
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/761 , H01L21/76248
摘要： A semiconductor device and method of fabrication using LEGO (Lateral Epitaxial Growth over Oxide) for forming a SOI (Silicon On Insulator) structure (FIG. 1) having a localized buried dielectric layer (2). By patterning the buried dielectric layer, covered with a thin polysilicon layer by way of an epitaxial reactor a thick semiconductor layer (3) over the buried layer (2) is deposited. By rapid thermal annealing the polycrystalline overlayer is transformed into a single crystal layer (3). The buried oxide layer (2) provides a vertical dielectrical insulation, and deep diffused or trench regions (4, 5) provide lateral junction insulation. In this manner the SOI area (3) localized between the two deep diffused regions (4, 5) is fully insulated from the silicon substrate (1). This provides the following advantages: the process can be easily integrated in standard wafer fabrication equipment and processing techniques; the process is fully compatible with many existing technologies and their process flow; and low processing cost and low density defectivity should result.
摘要翻译：一种使用LEGO（横向外延生长在氧化物上）的半导体器件和制造方法，用于形成具有局部掩埋介电层（2）的SOI（绝缘体上硅）结构（图1）。通过利用外延反应器对覆盖有薄多晶硅层的掩埋介质层进行构图，沉积在掩埋层（2）上的厚半导体层（3）。通过快速热退火，多晶覆层转变为单晶层（3）。掩埋氧化物层（2）提供垂直的介电绝缘，并且深度扩散或沟槽区域（4,5）提供横向结合绝缘。以这种方式，位于两个深扩散区域（4,5）之间的SOI区域（3）与硅衬底（1）完全绝缘。这提供了以下优点：该方法可以容易地集成在标准晶圆制造设备和加工技术中; 该过程与许多现有技术及其工艺流程完全兼容; 导致加工成本低，密度低的缺点。

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