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31. 发明公开

EP1148651A3 Coding apparatus and coding method 审中-公开
标题翻译：编码和编码
公开(公告)号：EP1148651A3
公开(公告)日：2004-09-01
申请号：EP01302998.8
申请日：2001-03-29
申请人： SONY CORPORATION
发明人： Hattori, Masayuki , Murayama, Jun , Miyauchi, Toshiyuki , Yamatomo, Kouhei , Yokokawa, Takashi
IPC分类号： H03M13/29 , H03M13/25 , H03M13/27 , H03M13/23 , H03M13/45 , H04L1/00
CPC分类号： H03M13/256 , H03M13/258 , H03M13/2972 , H03M13/3988
摘要： To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

32. 发明公开

EP1148651A2 Coding apparatus and coding method 审中-公开
标题翻译： Kodiervorrichtung und Kodierverfahren
公开(公告)号：EP1148651A2
公开(公告)日：2001-10-24
申请号：EP01302998.8
申请日：2001-03-29
申请人： SONY CORPORATION
发明人： Hattori, Masayuki , Murayama, Jun , Miyauchi, Toshiyuki , Yamatomo, Kouhei , Yokokawa, Takashi
IPC分类号： H03M13/29 , H03M13/23 , H03M13/45
CPC分类号： H03M13/256 , H03M13/258 , H03M13/2972 , H03M13/3988
摘要： To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.
摘要翻译：根据串行级联的编码调制系统进行纠错编码和解码，具有小的电路规模和高性能。编码装置1被设计成使得交织器20交织比特的顺序，使得所有权重相对于包括从卷积编码器10提供的一系列3比特的数据由卷积编码器30编码; 卷积编码器30相对于从交织器20提供的3比特的数据，尽可能地使输入比特的汉明距离的总值为最小欧几里德距离; 并且多值调制映射电路40使得卷积编码器30中的输入比特的汉明距离随着I / Q平面上的信号点之间的距离变小，从卷积编码器30提供的3比特数据映射。

33. 发明公开

EP0924863A2 Viterbi decoding apparatus and viterbi decoding method 审中-公开
标题翻译：维特比 - 德科迪亚诺
公开(公告)号：EP0924863A2
公开(公告)日：1999-06-23
申请号：EP98124034.4
申请日：1998-12-17
申请人： SONY CORPORATION
发明人： Hattori, Masayuki , Miyauchi, Toshiyuki
IPC分类号： H03M13/00
CPC分类号： H03M13/6583 , H03M13/4107 , H03M13/4123 , H03M13/4161 , H03M13/4176
摘要： A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register 1021 in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.
摘要翻译：除了与每个状态相对应地布置有与切割长度一样多的存储器单元串之外，还提供了一个寄存器列。对应于状态00的寄存器列中的各个级的选择器的输出被输入到寄存器列表和选择器中的寄存器1021。前级寄存器的输出分别输入到这三个选择器。当接收字终止时，根据控制电路的控制，在其他情况下，三个选择器将输出切换到后级。因此，当接收字终止时，存储在寄存器列表中的信息被原样传送。通过这样的操作，当接收字终止时，可以解码达到状态00的路径。

34. 发明授权

EP2256974B1 LDPC decoding method and apparatus 有权
标题翻译：一种用于LDPC解码和相应的设备过程
公开(公告)号：EP2256974B1
公开(公告)日：2014-01-01
申请号：EP10004802.4
申请日：2010-05-06
申请人： Sony Corporation
发明人： Kishimoto, Naomichi , Matsumoto, Hideyuki , Miyauchi, Toshiyuki , Mizutani, Yuichi
IPC分类号： H03M13/11 , H04L1/00 , H03M13/37
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/3715 , H03M13/6552 , H04L1/0053 , H04L1/0057

35. 发明公开

EP2270989A3 Decoding apparatus, decoding method, and program 有权
标题翻译：解码装置，解码方法和程序
公开(公告)号：EP2270989A3
公开(公告)日：2011-06-22
申请号：EP10178005.4
申请日：2004-04-19
申请人： Sony Corporation
发明人： Yokokawa, Takashi , Miyauchi, Toshiyuki , Iida, Yasuhiro
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译：本发明涉及用于实现LDPC码的解码的解码装置和解码方法，其中，在抑制电路规模的同时，可以将操作频率抑制在足够可行的范围内，并且可以执行对存储器访问的控制很容易，并为此编程。 LDPC码的校验矩阵由（P×P）单位矩阵，单位矩阵的1到几个1被替换为0的矩阵，它们被循环移位的矩阵，矩阵，这是它们中的两个或更多个的总和，以及（P×P）0矩阵。校验节点计算器313同时执行p校验节点计算。变量节点计算器319同时执行p个变量节点计算。

36. 发明公开

EP2169893A3 Determination of a starting point of the FFT window in an OFDM receiver 有权
标题翻译：确定FFT窗口的开始点在OFDM接收机
公开(公告)号：EP2169893A3
公开(公告)日：2011-01-12
申请号：EP09252278.8
申请日：2009-09-25
申请人： Sony Corporation
发明人： Kawauchi, Hidetoshi c/oSony Coriporation , Hattori, Masayuki c/o Sony Corportion , Yokokawa, Takashi c/o Sony Corportation , Shimizu, Kazuhiro c/o Sony Corportion , Funamoto,Kazuhisa c/o Sony Corporation , Miyauchi, Toshiyuki
IPC分类号： H04L27/26 , H04L25/02
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： A receiving apparatus includes: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section is configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

37. 发明公开

EP2256974A2 LDPC decoding method and apparatus 有权
标题翻译： Verfahren zur LDPC Dekodierung und entsprechende Einrichtung
公开(公告)号：EP2256974A2
公开(公告)日：2010-12-01
申请号：EP10004802.4
申请日：2010-05-06
申请人： Sony Corporation
发明人： Kishimoto, Naomichi , Matsumoto, Hideyuki , Miyauchi, Toshiyuki , Mizutani, Yuichi
IPC分类号： H04L1/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/3715 , H03M13/6552 , H04L1/0053 , H04L1/0057
摘要： Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode a low density parity check code; and a speed control section configured to control a speed of the decoding on the basis of a reception interval of the low density parity check code.
摘要翻译：本文公开了一种接收装置，包括：解码部分，被配置为接收和解码低密度奇偶校验码; 以及速度控制部，其被配置为基于所述低密度奇偶校验码的接收间隔来控制所述解码的速度。

38. 发明公开

EP1689085A3 Error correction with iterations of belief propagation decoding and algebraic decoding 审中-公开
标题翻译：与信仰Propagation-和代数解码的迭代Fehlercorrektur
公开(公告)号：EP1689085A3
公开(公告)日：2007-05-09
申请号：EP06002499.9
申请日：2006-02-07
申请人： SONY CORPORATION
发明人： Kan, Makiko , Miyauchi, Toshiyuki
IPC分类号： H03M13/45
CPC分类号： H03M13/1191 , H03M13/132 , H03M13/1515 , H03M13/152 , H03M13/3746 , H03M13/453
摘要： An ABP (Adaptive Belief Propagation) decoding apparatus (31) for decoding error correction codes such as RS, BCH or AG codes diagonalizes a parity check matrix, updates LLR values, decodes the LLR values using a soft or hard algebraic decoding algorithm and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus (31) repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus (31) successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus (31) selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding.

39. 发明公开

EP1739843A2 Viterbi decoding 有权
标题翻译： Leistungseffizienter维特比Dekoder
公开(公告)号：EP1739843A2
公开(公告)日：2007-01-03
申请号：EP06253258.5
申请日：2006-06-23
申请人： SONY CORPORATION
发明人： Miyauchi, Toshiyuki , Mizutani, Yuichi
IPC分类号： H03M13/41
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.
摘要翻译：本发明可以减少跟踪时的功耗。本发明提供了一种用于对卷积码进行解码的维特比解码装置，该维特比解码装置包括一个路径存储单元，该路径存储单元存储朝向卷积码的各个转换状态的两个路径之一作为多个连续时间点的所选路径，跟踪单元其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元，路径存储单元，其中，所述路径存储单元具有被设计为存储在各个时间点处各自的转变状态的所选择的路径的存储区域，所述存储区域被划分为从所述过渡状态的最低阶的子区域，每个所述子区域对应于预定数量的比特，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域在各个时间点读取数据，以停止从指定的子区域读取数据。

40. 发明公开

EP1496519A3 Encoding method and memory apparatus 有权
标题翻译： Kodierungsverfahren und Speicheranordnung
公开(公告)号：EP1496519A3
公开(公告)日：2005-02-09
申请号：EP04023697.8
申请日：1999-01-21
申请人： Sony Corporation
发明人： Miyauchi, Toshiyuki , Hattori, Masayuki
IPC分类号： G11C29/00 , G11C11/56
CPC分类号： G06F11/1008 , G06F11/1068 , G06F11/1072 , G11C7/1006 , G11C11/56 , G11C11/5621 , G11C16/04 , G11C29/00 , G11C29/42 , H03M13/15
摘要： This invention relates to a memory apparatus or the like adaptable to a multi-value recording flash memory and others. A flash memory 10 is designed for 16-value (4-bit) recording. For a write operation, the encoder (12) converts input data Din into an abbreviated Reed-Solomon code to provide write data WD. The converter (13) converts the write data WD into four-bit parallel data. The converted data are fed and written to the each memory cell constituting cell arrays (11) successively. For a read operation, the converter (14) converts read data RD from the cell arrays (11) into one-byte (8-bit) parallel data and supplies the converted data to the decoder (15) for error correction in units of bytes, whereby output data Dout is obtained. Since the Reed-Solomon code is used, sufficient performance with a limited number of errors to be corrected can be obtained.
摘要翻译：本发明涉及适用于多值记录闪存等的存储装置等。闪存10被设计用于16值（4位）记录。对于写入操作，编码器（12）将输入数据Din转换为缩写的Reed-Solomon码，以提供写入数据WD。转换器（13）将写入数据WD转换为四位并行数据。转换后的数据被依次送入构成单元阵列（11）的各存储单元。对于读取操作，转换器（14）将来自单元阵列（11）的读取数据RD转换成一个字节（8位）的并行数据，并将转换的数据提供给解码器（15），用于以字节为单位进行纠错，从而获得输出数据Dout。由于使用里德 - 所罗门码，所以可以获得具有有限数量的错误的足够的性能。

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