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31. 发明公开

EP0459502A3 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：EP0459502A3
公开(公告)日：1993-01-13
申请号：EP91108897.9
申请日：1991-05-31
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Tokonami, Katsuji , Ohshima, Shigeo
IPC分类号： H01L23/50 , H01L23/485
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014 , H01L2924/14 , H01L2224/45099 , H01L2224/05599
摘要： There is disclosed a semiconductor integrated circuit device having: external input signal leads (109A,B) provided outside a semiconductor chip (201); a power supply lead (108) provided outside the semiconductor chip (201); a first electrode (104A) connected to an internal circuit (102A) on the semiconductor chip (201), and arranged close to the external input signal lead (109A), wherein when the circuit (102A) is caused to be operative, the first electrode (104A) is connected to the external input signal lead (109A); and a second electrode (105A) connected to the first electrode (104A) on the semiconductor chip (201), and arranged close to said power supply lead (108), wherein when the circuit (102A) is not caused to be operative, the second electrode (105A) is connected to the power supply lead (108). This invention is also applicable to a device where there are provided a plurality of internal circuits (102a, 102b). In this case, a plurality of the first electrodes (104a, 104b) drawn out from the internal circuits (102A,102B) are arranged close to the external input signal lead (109A,109B), and a plurality of the second electrodes (105a, 105b) similarly drawn out from the internal circuits (102A,102B) are arranged close to the power supply lead (108).
摘要翻译：公开了一种半导体集成电路器件，其具有设置在半导体芯片的外部的外部输入信号引线（109）设置在所述半导体芯片外部的电源引线（108）连接到半导体芯片上的内部电路（102）并且靠近外部输入信号引线设置的第一电极（104），其中当使电路工作时，第一电极连接到外部输入信号引线 ; 以及连接到半导体芯片上的第一电极并且靠近所述电源引线设置的第二电极（105），其中当不使电路工作时，第二电极连接到电源引线。本发明适用于设置有多个内部电路（102a，102b）的装置。在这种情况下，从内部电路引出的多个第一电极（104a，104b）布置成靠近外部输入信号引线，并且多个第二电极（105a，105b）类似地从内部电路中抽出靠近电源线安排。

32. 发明公开

EP0460692A3 Semiconductor memory with failure handling circuit 失效
标题翻译：具有故障处理电路的半导体存储器
公开(公告)号：EP0460692A3
公开(公告)日：1992-11-19
申请号：EP91109340.9
申请日：1991-06-07
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/46 , G11C7/1075 , G11C29/003 , G11C29/02
摘要： The disclosed semiconductor memory comprises a random access memory port (73), a serial access memory port (71), a data transfer gate (11) formed between the two ports, and in particular a test signal generating circuit (12) for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

33. 发明公开

EP0432509A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0432509A3
公开(公告)日：1992-09-30
申请号：EP90121917.0
申请日：1990-11-15
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kiryu, Masakazu , Ohshima, Shigeo
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/00 , G11C11/4096
摘要： A semiconductor memory device comprises a memory cell array, a row decoder (RD), a column decoder (CP1), registers (CR) and a control unit (BLW). The control unit (BLW) allows the write operational mode of the column decoder (CD1) to switch. In the ordinary write operational mode, data in the n registers (CR) are written into the active memory cells of the n memory cell columns in one column block (CB) selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2 N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units (UNT). Each memory unit (UNT) comprises a memory cell array, a row decoder (RD), a first column decoder (CP1), a second column decoder (CD2), a data input terminal (WI/O), registers (CR) and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register (CR) is written into one memory cell (MC) connected to one word line (WL) selected by the row decoder (RD) of one column selected by the first column decoder (CD1) of column blocks (CB) selected by the second decoder (CD2). While when the device is in the block write mode, data latched in the register (CR) is written at the same time into j memory cells (MC) connected to one word line (WL) selected by the row decoder (RD) of column blocks (CB) selected by the second column decoder (CD2).
摘要翻译：半导体存储器件包括存储单元阵列，行解码器（RD），列解码器（CP1），寄存器（CR）和控制单元（BLW）。控制单元（BLW）允许列解码器（CD1）的写操作模式切换。在普通写入操作模式中，n个寄存器（CR）中的数据分别被写入由列解码器选择的一个列块（CB）中的n个存储器单元列的活动存储器单元中。在块写入模式中，将n个寄存器中的数据分别写入由列解码器选择的2N个列块中的n个存储器单元列中的有效存储器单元。另一种半导体存储器件包括N个存储单元（UNT）。每个存储单元（UNT）包括存储单元阵列，行解码器（RD），第一列解码器（CP1），第二列解码器（CD2），数据输入端子（WI / O），寄存器（CR）和一个控制电路。控制电路可操作以允许操作模式。当器件处于普通模式时，锁存在寄存器（CR）中的数据被写入连接到由第一列选择的一列的行解码器（RD）选择的一个字线（WL）的一个存储器单元（MC）由第二解码器（CD2）选择的列块（CB）的解码器（CD1）。而当器件处于块写入模式时，锁存在寄存器（CR）中的数据同时写入连接到由列的行解码器（RD）选择的一个字线（WL）的j个存储器单元（MC）由第二列解码器（CD2）选择的块（CB）。

34. 发明公开

EP0359203A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0359203A3
公开(公告)日：1992-02-26
申请号：EP89116871.8
申请日：1989-09-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/409 , G11C11/408
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096
摘要： Memory cells (12,22...N2) disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by first gate means. One memory cell column in the n memory cell columns in a selected block is selected by second gate means. One memory cell (12,22...N2) in a selected memory cell column is selected by a row address. The data in a selected memory cell (12,22...N2) are stored in a register and output therefrom.
摘要翻译：设置在矩阵中的存储单元（12,22 ... N2）被分成多个块。每个块由n（n是大于2的正整数）个存储单元列构成。一个块由一个列地址选择。通过第一门装置选择所选块中的n个存储单元列中的一个存储单元列。通过第二门装置选择所选块中的n个存储单元列中的一个存储单元列。所选存储单元列中的一个存储单元（12,22 ... N2）由行地址选择。选定存储单元（12,22 ... N2）中的数据被存储在寄存器中并从其中输出。

35. 发明公开

EP0464468A2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0464468A2
公开(公告)日：1992-01-08
申请号：EP91110045.1
申请日：1991-06-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Miyamoto, Shinji , Ohshima, Shigeo
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , G11C7/1051
摘要： A semiconductor memory device having: a first power source (P1) having a non-ground potential V cc1 terminal and a ground potential V ss1 terminal;
the internal circuit (10) being supplied with power from the power source (P1) dedicated to the internal circuit, the internal circuit selecting a memory cell (MC) of a memory cell array (4) in accordance with an inputted address (A1, A2) and having a first output terminal (1) and a second output terminal (2), and the first output terminal outputting one of the pair of potentials V cc1 and V ss1 and the second output terminal outputting the other of the pair, in accordance with the data in the selected memory cell; a second power source (P2) output circuit (20) and having a non-ground potential V cc2 terminal and a ground potential V ss2 terminal; and the output circuit being supplied with power from the power source dedicated to the output circuit, the output circuit having first and second transistors (T1, T0) serially connected between the V cc2 terminal and V ss2 terminal, the control terminals of the first and second transistors being connected to the first and second output terminals (1, 2), and having a third transistor (T2) being connected between an interconnection between the first and second transistors connected to a data output terminal (D out ) from which data is externally outputted, and the first output terminal, and the control terminal of the third transistor being connected to the second output terminal (2).
摘要翻译：一种半导体存储器件，具有：具有非接地电位Vcc1端子和接地电位Vss1端子的第一电源（P1）内部电路（10）由专用于内部电路的电源（P1）供电，内部电路根据输入的地址（A1，A1）选择存储单元阵列（4）的存储单元（MC） A2）并且具有第一输出端子（1）和第二输出端子（2），并且第一输出端子输出一对电位Vcc1和Vss1中的一个，并且第二输出端子输出另一个电位，根据所选存储单元中的数据; 第二电源（P2）输出电路（20），具有非接地电位Vcc2端子和接地电位Vss2端子; 并且输出电路由专用于输出电路的电源供电，输出电路具有串联连接在Vcc2端子和Vss2端子之间的第一和第二晶体管（T1，T0），第一和第二晶体管连接到所述第一和第二输出端子，并且具有第三晶体管，所述第三晶体管连接在连接到从外部输出数据的数据输出端子的第一和第二晶体管之间的互连之间，和第一输出端子，并且第三晶体管的控制端子连接到第二输出端子（2）。

36. 发明公开

EP0460692A2 Semiconductor memory with failure handling circuit 失效
标题翻译： Halbleiterspeicher mit Fehlerbehandlungsschaltung。
公开(公告)号：EP0460692A2
公开(公告)日：1991-12-11
申请号：EP91109340.9
申请日：1991-06-07
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/46 , G11C7/1075 , G11C29/003 , G11C29/02
摘要： The disclosed semiconductor memory comprises a random access memory port (73), a serial access memory port (71), a data transfer gate (11) formed between the two ports, and in particular a test signal generating circuit (12) for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.
摘要翻译：所公开的半导体存储器包括随机存取存储器端口（73），串行存取存储器端口（71），形成在两个端口之间的数据传输门（11），特别是用于产生测试信号到数据传输门以关闭门，使得存储在串行存取存储器端口中的数据可以读取到外部，而不将数据从随机存取存储器端口传送到串行存取存储器端口。因此，可以区分从串行存取存储器端口读取数据时所引起的错误操作与从数据从随机存取存储器端口传送到串行访问存储器端口时引起的错误操作。

37. 发明公开

EP0420268A2 Function selector circuit 失效
标题翻译： Betriebsartenwählerschaltung。
公开(公告)号：EP0420268A2
公开(公告)日：1991-04-03
申请号：EP90118680.9
申请日：1990-09-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C7/1015
摘要： A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
摘要翻译：功能选择电路包括用于产生对应于多个输入信号状态的所有组合中的每一个的多个第一信号的第一信号发生电路（2）以及第二信号发生电路（5），用于选择多个第一信号的组合的多个逻辑和，并且产生与选择性地激活由真值表指示的操作功能的多个逻辑和中的每一个对应的第二信号。

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