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21. 发明公开

EP0762288A2 Prefetching data cache 失效
标题翻译： Cachespeicher mit Datenvorausladung
公开(公告)号：EP0762288A2
公开(公告)日：1997-03-12
申请号：EP96305419.2
申请日：1996-07-24
申请人： International Business Machines Corporation
发明人： Mayfield, Michael J.
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0897 , G06F2212/6022 , G06F2212/6026
摘要： Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time.
摘要翻译：在实现L1和L2高速缓存以及流过滤器和缓冲器的数据处理系统内，以渐进方式执行高速缓存行的预取。在一种模式下，数据可能不会被预取。在第二模式中，预取两条高速缓存行，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。

22. 发明公开

EP0646870A1 Information processing system including a cache and means for prefetching data 失效
标题翻译：具有超高速缓冲存储器和用于Datenvorausholung一个装置的信息处理系统。
公开(公告)号：EP0646870A1
公开(公告)日：1995-04-05
申请号：EP94306614.2
申请日：1994-09-08
申请人： International Business Machines Corporation
发明人： Kahle, James Allan
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3834 , G06F12/0811 , G06F12/0862 , G06F2212/6022 , G06F2212/6028
摘要： An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.
摘要翻译：一种信息处理系统10包括用于处理指令的处理器10，系统存储器30，高速缓冲存储器12，以及补充26.针对第一指令，该辅助存储器存储来自系统存储器的第一信息。响应于第二指令，如果所述第一信息包括所述第二信息，并且从系统存储器否则高速缓冲存储器存储来自辅助存储器的第二信息。

23. 发明公开

EP3321810A1 PROCESSOR WITH INSTRUCTION CACHE THAT PERFORMS ZERO CLOCK RETIRES 有权
标题翻译：带有指令高速缓存的处理器，可执行零时钟退货
公开(公告)号：EP3321810A1
公开(公告)日：2018-05-16
申请号：EP16203899.6
申请日：2016-12-13
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： BEAN, Brent
IPC分类号： G06F12/0855 , G06F12/0882 , G06F12/0895 , G06F12/0862 , G06F9/38 , G06F12/1045
CPC分类号： G06F12/023 , G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F12/0855 , G06F12/0859 , G06F12/0862 , G06F12/0875 , G06F12/0882 , G06F12/0895 , G06F12/1054 , G06F2212/1024 , G06F2212/1044 , G06F2212/452 , G06F2212/601 , G06F2212/6022 , G06F2212/6026
摘要： A method of retiring cache lines from a response buffer array to an icache array of a processor including providing sequential addresses to the icache array and to a response buffer array during successive clock cycles, detecting a first address hitting the response buffer array during a first clock cycle, during a second clock cycle that follows the first clock cycle, performing a first zero clock retire to write a first cache line from the response buffer array to the icache array, and during the second clock cycle, bypassing a second address which is one of the sequential addresses. The second address is bypassed given the assumption that it will likely hit the response buffer array in a subsequent cycle. If the second address missed the response buffer array, the bypassed address is replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.
摘要翻译：一种将高速缓存线从响应缓冲器阵列撤回到处理器的icache阵列的方法，包括在连续时钟周期期间向icache阵列和响应缓冲器阵列提供连续地址，检测在第一时钟期间击中响应缓冲器阵列的第一地址在第一时钟周期之后的第二时钟周期期间，执行第一零时钟休眠以将第一高速缓存线从响应缓冲器阵列写入到ICache阵列，并且在第二时钟周期期间，绕过第一时钟周期的第二地址的顺序地址。考虑到它可能会在后续周期中响应响应缓冲区阵列，第二个地址被绕过。如果第二个地址错过了响应缓冲区阵列，则绕过的地址会被重播并带有轻微的时间损失，这可以通过零时钟退休时间的节省超过。

24. 发明授权

EP2908248B1 MEMORY DATA PUSHING METHOD AND DEVICE 有权
标题翻译：存储器数据推送方法和装置
公开(公告)号：EP2908248B1
公开(公告)日：2017-09-20
申请号：EP13845440.0
申请日：2013-06-05
申请人： Huawei Technologies Co., Ltd.
发明人： CHEN, Mingyang , CHEN, Mingyu , CUI, Zehan , CHEN, Licheng
IPC分类号： G06F12/0862 , G06F17/30
CPC分类号： G06F12/0862 , G06F12/0866 , G06F17/30132 , G06F2212/1024 , G06F2212/312 , G06F2212/602 , G06F2212/6022 , G06F2212/6028

25. 发明授权

EP2396790B1 MEMORY PREFETCH SYSTEMS AND METHODS 有权
标题翻译：存储器预取系统和方法
公开(公告)号：EP2396790B1
公开(公告)日：2017-08-23
申请号：EP10741802.2
申请日：2010-02-12
申请人： Micron Technology, Inc.
发明人： JEDDELOH, Joe, M.
IPC分类号： G06F1/32 , G06F12/0862 , G06F13/16
CPC分类号： G06F12/0875 , G06F1/3203 , G06F1/3275 , G06F12/0862 , G06F2212/6022 , Y02D10/13 , Y02D10/14
摘要： Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty.
摘要翻译：本文公开了系统和方法，包括当与所选存储器库相关联的流水线为空时用于从堆叠裸片存储器系统中的选定存储器库预取可编程数量的数据字的系统和方法。

26. 发明公开

EP2908248A1 MEMORY DATA PUSHING METHOD AND DEVICE 有权
标题翻译： VICHRICHTUNG的SPEICHERDATENWEITERLEITUNGSVERFAHREN
公开(公告)号：EP2908248A1
公开(公告)日：2015-08-19
申请号：EP13845440.0
申请日：2013-06-05
申请人： Huawei Technologies Co., Ltd.
发明人： CHEN, Mingyang , CHEN, Mingyu , CUI, Zehan , CHEN, Licheng
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0866 , G06F17/30132 , G06F2212/1024 , G06F2212/312 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
摘要： Embodiments of the present invention provide a method and an apparatus for pushing memory data. The method includes: periodically generating a push command according to a push period, where one push command is periodically generated within one push period; acquiring a push parameter of to-be-pushed data according to the push command; sending at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory; receiving the to-be-pushed data that is sent according to the memory access request by the memory, and placing, in a data buffer, the to-be-pushed data that is sent according to the memory access request by the memory; and pushing the to-be-pushed data from the data buffer to the push destination storage.
摘要翻译：本发明的实施例提供一种用于推动存储器数据的方法和装置。该方法包括：根据推送周期周期性地产生推送命令，其中在一个推送周期内周期性地产生一个推送命令; 根据推送命令获取被推送数据的推送参数; 根据所述推送参数向存储器发送至少一个存储器访问请求，其中所述至少一个存储器访问请求用于从所述存储器请求所述待推送数据; 接收由所述存储器根据所述存储器访问请求而被发送的所述被推送数据，以及在所述存储器中将根据所述存储器访问请求发送的所述被推送数据放置在数据缓冲器中; 并将待推送数据从数据缓冲器推送到推送目的地存储器。

27. 发明公开

EP2457168A1 SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR 审中-公开
标题翻译：信号处理系统，带有缓冲控制逻辑及其方法集成电路
公开(公告)号：EP2457168A1
公开(公告)日：2012-05-30
申请号：EP09847522.1
申请日：2009-07-20
申请人： Freescale Semiconductor, Inc.
发明人： ROBERTSON, Alistair , CIRCELLO, Joseph , Maiolani, Mark
IPC分类号： G06F13/16 , G06F5/00
CPC分类号： G06F12/0862 , G06F9/3804 , G06F9/3814 , G06F12/123 , G06F12/127 , G06F2212/6022
摘要： A signal processing system (100) comprising buffer control logic (142) arranged to allocate a plurality of buffers (144) for the storage of information fetched from at least one memory element (160). Upon receipt of fetched information to be buffered, the buffer control logic (142) is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer (144) for the storage of the fetched information to be buffered.

28. 发明公开

EP2447829A2 Prefetch instruction 审中-公开
标题翻译： Vorabrufanweisung
公开(公告)号：EP2447829A2
公开(公告)日：2012-05-02
申请号：EP11186927.7
申请日：2011-10-27
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/30047 , G06F12/0837 , G06F12/0862 , G06F2212/6022
摘要： Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained.
摘要翻译：公开了关于从存储器预取数据的技术。在一个实施例中，集成电路可以包括包含执行核心和数据高速缓存的处理器。执行核心可以被配置为接收指定从其检索数据的存储器地址的预取指令的实例。响应于指令的实例，执行核心从存储器地址检索数据并将其存储在数据高速缓存中的数据中，而不管对应于该特定存储器地址的数据是否已经存储在数据高速缓存中。以这种方式，可以将数据高速缓存用作存储器缓冲器中未保持相干性的数据的预取缓冲器。

29. 发明授权

EP1999574B1 DATA PROCESSOR HAVING DYNAMIC CONTROL OF INSTRUCTION PREFETCH BUFFER DEPTH AND METHOD THEREFOR 有权转让
标题翻译：订购时ADVANCE LOAD缓存深度的方法及其动态控制信息处理
公开(公告)号：EP1999574B1
公开(公告)日：2012-04-11
申请号：EP07757384.8
申请日：2007-02-23
申请人： Freescale Semiconductor, Inc.
发明人： SCOTT, Jeffrey W. , MOYER, William C.
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).

30. 发明授权

EP1573555B1 PAGE DESCRIPTORS FOR PREFETCHING AND MEMORY MANAGEMENT 有权
标题翻译：页面描述符VORAUSHOLUNG和内存管理
公开(公告)号：EP1573555B1
公开(公告)日：2010-07-21
申请号：EP03780378.0
申请日：2003-12-11
申请人： International Business Machines Corporation
发明人： FRANASZEK, Peter
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024

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