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1. 发明公开

EP2447829A2 Prefetch instruction 审中-公开
标题翻译： Vorabrufanweisung
公开(公告)号：EP2447829A2
公开(公告)日：2012-05-02
申请号：EP11186927.7
申请日：2011-10-27
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/30047 , G06F12/0837 , G06F12/0862 , G06F2212/6022
摘要： Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained.
摘要翻译：公开了关于从存储器预取数据的技术。在一个实施例中，集成电路可以包括包含执行核心和数据高速缓存的处理器。执行核心可以被配置为接收指定从其检索数据的存储器地址的预取指令的实例。响应于指令的实例，执行核心从存储器地址检索数据并将其存储在数据高速缓存中的数据中，而不管对应于该特定存储器地址的数据是否已经存储在数据高速缓存中。以这种方式，可以将数据高速缓存用作存储器缓冲器中未保持相干性的数据的预取缓冲器。

2. 发明授权

EP2533520B1 Image sensor having HDR capture capability 有权
标题翻译：具有高动态范围图像传感器
公开(公告)号：EP2533520B1
公开(公告)日：2016-10-12
申请号：EP12171184.0
申请日：2012-06-07
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： H04N5/353 , H04N5/355 , H04N5/235
CPC分类号： H04N5/35554 , H04N5/2355 , H04N5/3532 , H04N5/35536

3. 发明公开

EP2533520A2 Image sensor having HDR capture capability 有权
标题翻译： Bildsensor mit einem hohen dynamischen Bereich
公开(公告)号：EP2533520A2
公开(公告)日：2012-12-12
申请号：EP12171184.0
申请日：2012-06-07
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： H04N5/355
CPC分类号： H04N5/35554 , H04N5/2355 , H04N5/3532 , H04N5/35536
摘要： An apparatus comprising:
an image processing circuit comprising:
a data path configured to transmit image data related to multiple exposures of a single image;
an image signal processor coupled to the data path, wherein the image signal processor is configured to receive the image data and to separate the image data into at least two categories based on at least one criteria; and
a first buffer coupled to the image signal processor and configured to store data from at least one of the categories.
摘要翻译：一种装置，包括：图像处理电路，包括：数据路径，被配置为发送与单个图像的多次曝光有关的图像数据; 耦合到所述数据路径的图像信号处理器，其中所述图像信号处理器被配置为接收所述图像数据，并且基于至少一个准则将所述图像数据分离成至少两个类别; 以及耦合到所述图像信号处理器并被配置为存储来自所述类别中的至少一个的数据的第一缓冲器。

4. 发明公开

EP2533520A3 Image sensor having HDR capture capability 有权
标题翻译：具有高动态范围图像传感器
公开(公告)号：EP2533520A3
公开(公告)日：2013-07-24
申请号：EP12171184.0
申请日：2012-06-07
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： H04N5/355 , H04N5/235
CPC分类号： H04N5/35554 , H04N5/2355 , H04N5/3532 , H04N5/35536
摘要： An apparatus comprising:
an image processing circuit comprising:
a data path configured to transmit image data related to multiple exposures of a single image;
an image signal processor coupled to the data path, wherein the image signal processor is configured to receive the image data and to separate the image data into at least two categories based on at least one criteria; and
a first buffer coupled to the image signal processor and configured to store data from at least one of the categories.

5. 发明公开

EP2447829A3 Prefetch instruction 审中-公开
标题翻译：预取指令
公开(公告)号：EP2447829A3
公开(公告)日：2012-11-14
申请号：EP11186927.7
申请日：2011-10-27
申请人： Apple Inc.
发明人： Frank, Michael
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F9/383 , G06F9/30047 , G06F12/0837 , G06F12/0862 , G06F2212/6022
摘要： Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained.
摘要翻译：公开了与从存储器预取数据有关的技术。在一个实施例中，集成电路可以包括含有执行核心和数据高速缓存的处理器。执行核心可以被配置为接收指定从中检索数据的存储器地址的预取指令的实例。响应于该指令的实例，执行核心从存储器地址中检索数据并将其存储在数据高速缓存中的数据中，而不管与该特定存储器地址对应的数据是否已经存储在数据高速缓存中。以这种方式，数据高速缓冲存储器可以被用作存储器缓冲器中的数据的预取缓冲器，其中一致性尚未被保持。

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