专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0624837A1 Electronic apparatus with reduced power consumption 失效
标题翻译： ElektronischesGerätmit verminderer Leistungsaufnahme。
公开(公告)号：EP0624837A1
公开(公告)日：1994-11-17
申请号：EP94302709.4
申请日：1994-04-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alexander, Michael Clay , Arizpe, Arturo Lopez , Gerosa, Gianfranco , Kahle, James Allan , Ogden, Aubrey Deene
IPC分类号： G06F1/32
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.
摘要翻译：提供了一种方法和电路，其中利用第一电路执行第一操作。用第二电路执行第二操作。响应于第一操作产生第一信号。响应于第二操作产生第二信号。响应于第一和第二信号，在第二电路内调节功耗。

2. 发明授权

EP0646870B1 Information processing system including a cache and means for prefetching data 失效
标题翻译：具有超高速缓冲存储器和用于Datenvorausholung一个设备的信息处理系统
公开(公告)号：EP0646870B1
公开(公告)日：2002-07-17
申请号：EP94306614.2
申请日：1994-09-08
申请人： International Business Machines Corporation
发明人： Kahle, James Allan
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3834 , G06F12/0811 , G06F12/0862 , G06F2212/6022 , G06F2212/6028

3. 发明公开

EP0624845A1 Information processing system comprising one or more cached devices 失效
标题翻译： Informationverarbeitungssystem mit einer oder mehreren Vorrichtungen mit Cachespeichern。
公开(公告)号：EP0624845A1
公开(公告)日：1994-11-17
申请号：EP94302793.8
申请日：1994-04-20
申请人： International Business Machines Corporation
发明人： Kahle, James Allan
IPC分类号： G06F12/08
CPC分类号： G06F12/0835
摘要： A method and system are provided for maintaining memory coherency. A memory device (16) stores information. A non-cached (18) is coupled to the memory device. The non-cached device inputs at least a portion of the information and outputs an indication that the portion is not to be cached by the non-cached device. At least one cached device (12,14) coupled to said memory device is responsive to said indication.
摘要翻译：提供了一种用于维持内存一致性的方法和系统。存储装置（16）存储信息。非高速缓存（18）耦合到存储器件。非缓存设备输入信息的至少一部分并且输出该部分不被非缓存设备高速缓存的指示。耦合到所述存储器设备的至少一个缓存设备（12,14）响应于所述指示。

4. 发明公开

EP0646870A1 Information processing system including a cache and means for prefetching data 失效
标题翻译：具有超高速缓冲存储器和用于Datenvorausholung一个装置的信息处理系统。
公开(公告)号：EP0646870A1
公开(公告)日：1995-04-05
申请号：EP94306614.2
申请日：1994-09-08
申请人： International Business Machines Corporation
发明人： Kahle, James Allan
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3834 , G06F12/0811 , G06F12/0862 , G06F2212/6022 , G06F2212/6028
摘要： An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.
摘要翻译：一种信息处理系统10包括用于处理指令的处理器10，系统存储器30，高速缓冲存储器12，以及补充26.针对第一指令，该辅助存储器存储来自系统存储器的第一信息。响应于第二指令，如果所述第一信息包括所述第二信息，并且从系统存储器否则高速缓冲存储器存储来自辅助存储器的第二信息。

5. 发明公开

EP0377991A3 Data processing systems 失效
标题翻译：数据处理系统
公开(公告)号：EP0377991A3
公开(公告)日：1991-07-31
申请号：EP89313401.5
申请日：1989-12-20
申请人： International Business Machines Corporation
发明人： Grohoski, Gregory Frederick , Kahle, James Allan , Nguyenphu, Myhong , Ray, David Scott
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/4812 , G06F9/3822 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3885
摘要： A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

6. 发明公开

EP0726526A3 Method and system for enhanced system management operation in a data processing system 失效
标题翻译：用于在数据处理系统中增强系统管理操作的方法和系统
公开(公告)号：EP0726526A3
公开(公告)日：1996-09-11
申请号：EP96480017.1
申请日：1996-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sell, John Victor , Kahle, James Allan , Ogden, Aubrey Deene , Loper, Albert J. , Mallick, Soummya
IPC分类号： G06F12/14 , G06F9/46
CPC分类号： G06F9/461 , G06F12/1475
摘要： A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.
摘要翻译：在超标量数据处理系统中用于增强系统管理操作的方法和系统。在受保护的存储器空间内执行选定的特许操作的那些监督级指令首先被识别为不需要完整的上下文同步。每次启动这样的指令的执行时，执行启用特殊访问（ESA）指令作为该指令或指令组的入口点。存储用于数据处理系统的机器状态寄存器的一部分，然后机器状态寄存器如下修改：设置问题位，将执行权限状态改变为“管理员”; 外部中断被禁止; 并设置访问权限状态位; 并设置特殊访问模式位，允许执行特殊指令。然后执行在受保护存储器空间内执行所选特许操作的指令。然后执行禁用特殊访问（DSA）指令，恢复机器状态寄存器中在ESA指令期间修改的位。 ESA和DSA指令是在不修改指令流的情况下通过利用用户级过程调用来实现的，由此减少了确定期望的执行路径所需的分支表的开销。

7. 发明公开

EP0726526A2 Method and system for enhanced system management operation in a data processing system 失效
标题翻译：方法和改进的系统管理的操作系统中的数据处理系统
公开(公告)号：EP0726526A2
公开(公告)日：1996-08-14
申请号：EP96480017.1
申请日：1996-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sell, John Victor , Kahle, James Allan , Ogden, Aubrey Deene , Loper, Albert J. , Mallick, Soummya
IPC分类号： G06F12/14 , G06F9/46
CPC分类号： G06F9/461 , G06F12/1475
摘要： A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.
摘要翻译：在超标量数据处理系统中的方法和用于增强的系统管理操作系统。其中执行所保护的存储空间内选择特权操作这些监控级别的指令首先识别为不需要完整的上下文同步。搜索指令的每次执行开始启用特殊接入（ESA）指令被执行为切入点，做了指令或指令组。用于数据处理系统中的机器状态寄存器的一部分被储存，然后在机器状态寄存器被修改如下：a问题位被设置，改变执行特权状态为“监;” 外部中断被禁止; 和访问权限状态位被设置; 并且，一个特殊的访问模式位时，允许的特殊指令的执行。其中执行受保护的内存空间中的选择特权操作的指令然后被执行。然后，禁止特殊访问（DSA）指令被执行，恢复哪ESA指令期间被修改的机器状态寄存器中的位。的ESA和DSA指令被实现，而不通过利用用户级别的过程调用，从而降低了分支表必要确定性矿井所需的执行路径的开销修改的指令流中。

8. 发明公开

EP0605874A1 Method and system for increased instruction dispatch efficiency in a superscalar processor system 失效
标题翻译：方法，以及用于命令分配系统在超标量处理机系统中的增加的效率。
公开(公告)号：EP0605874A1
公开(公告)日：1994-07-13
申请号：EP93120942.3
申请日：1993-12-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kahle, James Allan , Kau, Chin-Cheng , Levitan, David Steven , Ogden, Aubrey Deene
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3885
摘要： A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue (52) for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit (50) for dispatching instructions from an associated instruction buffer (54) to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer (54) is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer (54), the remaining instructions are shifted within the instruction buffer (54) in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer (54) from the instruction queue (52) utilizing a selectively controlled multiplex circuit (56-62). In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
摘要翻译：为提高指令调度效率在具有指令队列（52），用于在应用程序接收一组指令在超标量处理器系统中指定顺序和指令分派单元（50），用于从关于相关联的指令缓冲区调度指令的方法和系统（ 54）以在机会主义基础多个执行单元。的相关联的指令缓冲器（54）内的指令调度状态是周期性确定性开采和，响应于在所述指令缓冲器（54），剩余的指令在指令缓冲器内移动的开始的指令的调度（54）应用程序指定的顺序和指令的部分组被装载到从利用选择性控制的多路复用电路（56-62）指令队列（52）的指令缓冲器（54）。以这种方式附加指令可被调度到可用的执行单元，而无需先前组指令被完全发送。

9. 发明授权

EP0377991B1 Data processing systems 失效
公开(公告)号：EP0377991B1
公开(公告)日：1997-03-26
申请号：EP89313401.5
申请日：1989-12-20
申请人： International Business Machines Corporation
发明人： Grohoski, Gregory Frederick , Kahle, James Allan , Nguyenphu, Myhong , Ray, David Scott
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/4812 , G06F9/3822 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3885

10. 发明公开

EP0605873A1 Method and system for tracking scalar instructions within a superscalar processor system 失效
标题翻译： Verfahren und System zurÜberwachungvon Skalarbefehlen im superskalaren Prozessorsystem。
公开(公告)号：EP0605873A1
公开(公告)日：1994-07-13
申请号：EP93120941.5
申请日：1993-12-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kahle, James Allan , Waldecker, Donald Emil
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384
摘要： A method for tracking a group of scalar instructions within a superscalar data processor system. A group of unique identification numbers, which is large enough to uniquely identify each scalar instruction currently being executed within the superscalar data processor system, is selected (402). Thereafter, one of the unique identification numbers is associated (406) with each scalar instruction being processed within the superscalar processor system, as each scalar instruction is loaded (404) into the processor's instruction dispatcher. After the execution of a particular scalar instruction has completed (418), the association between the particular scalar instruction and the associated unique identification number is terminated (420), thereby allowing the group of unique identification numbers to be reutilized (422) to track subsequent scalar instruction execution within said superscalar data processor system.
摘要翻译：一种用于跟踪超标量数据处理器系统内的一组标量指令的方法。选择足够大以唯一地识别当前在超标量数据处理器系统内执行的每个标量指令的唯一识别号码组（402）。此后，随着每个标量指令被加载（404）到处理器的指令调度器中，唯一标识号之一被相关联（406），每个标量指令在超标量处理器系统内被处理。在特定标量指令的执行完成（418）之后，终止特定标量指令与相关联的唯一标识号之间的关联（420），从而允许重新使用唯一识别号码组（422）以跟踪后续所述超标量数据处理器系统内的标量指令执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式