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11. 发明公开

EP1366570A1 IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH ULTRA THIN VERTICAL BODY TRANSISTORS 审中-公开
标题翻译： WITH ULTRA THIN竖直主体TRANSISTORS运算可编程逻辑阵列
公开(公告)号：EP1366570A1
公开(公告)日：2003-12-03
申请号：EP02724909.3
申请日：2002-02-06
申请人： MICRON TECHNOLOGY, INC.
发明人： FORBES, Leonard
IPC分类号： H03K19/177 , H01L25/00 , G06F7/38
CPC分类号： H01L27/11803 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/66825 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for in service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. At least one single crystalline ultra thin vertical floating gate transistor that is disposed adjacent each vertical pillar. The single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A vertical floating gate opposes the ultra thin single crystalline vertical body region.

12. 发明公开

EP0820100A3 Semiconductor device and manufacturing method for the same, basic cell library and manufacturing method for the same, and mask 失效
标题翻译：半导体装置及其制造方法，初级细胞库和它们的生产方法和掩模
公开(公告)号：EP0820100A3
公开(公告)日：2001-05-16
申请号：EP97111750.2
申请日：1997-07-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yamaguchi, Akira
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L27/11803 , G03F1/36 , H01L27/0207
摘要： There are provided a semiconductor device, basic cell library, a method for manufacturing a semi-conductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effect correction (OPC), reduce the CAD processing time, perform correction by the OPC for each cell, and reduce the product turn around time. A basic cell registered in the basic cell library has a dummy wiring pattern (4, 41, 42, 43, 44) previously formed on the peripheral portion thereof. With this structure, the distance between a polysilicon gate (3) used in a circuit and the polysilicon wiring of an adjacent dummy wiring pattern in the basic cell can be determined in the cell. As a result, variations in the poly-widths of all of the polysilicon gates in the basic cell due to the optical proximity effect can be estimated, and therefore, a correction value by the OPC on a mask for correcting the gate width based on the variation in the poly-width can be determined in the cell.

13. 发明授权

EP0376291B1 Semiconductor integrated circuit 失效
标题翻译：的半导体集成电路
公开(公告)号：EP0376291B1
公开(公告)日：1997-06-04
申请号：EP89124039.2
申请日：1989-12-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakata, Shigeharu Intellectual Property Division , Andoh, Kazumasa Intellectual Property Division
IPC分类号： H01L27/02 , H01L27/118 , H01L23/50 , H01L23/528
CPC分类号： H01L23/5286 , H01L23/528 , H01L27/11803 , H01L2924/0002 , H01L2924/00

14. 发明公开

EP0161734A3 Integrated circuit architecture and fabrication method therefor 失效
标题翻译：集成电路架构及其制造方法
公开(公告)号：EP0161734A3
公开(公告)日：1987-02-04
申请号：EP85300498
申请日：1985-01-25
申请人： Integrated Logic Systems, Inc.
发明人： Taylor, David Lee
IPC分类号： H01L27/02 , H01L21/82
CPC分类号： H01L27/11803 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A new ensemble of logic elements organized in an array and a method of forming the same is described wherein the architecture includes a main field of transistor elements formed on a substrate material. A group of load transistors and an array of logic gates are formed on the substrate and are located within the main field of transistors. At least one routing channel is provided in the main field, and an input/output structure is located on the substrate. A region of flip-flop elements, also located within the main field, may be provided. Preferably, a plurality of such groups, arrays and regions are formed in parallel strips extending across the main field, and a perpendicular bussing channel also extends across the field to divide the main field into component arrays. The logic gates may be configurable structures or dedicated inverters, and a plurality of input/output structures may be employed. The method includes the electrical interconnection of these elements into logic terms to form an integrated circuit.

15. 发明授权

EP0046197B1 FET convolved logic 失效
标题翻译： FET卷积逻辑
公开(公告)号：EP0046197B1
公开(公告)日：1984-05-16
申请号：EP81105494.9
申请日：1981-07-14
申请人： International Business Machines Corporation
发明人： Rosenbluth, William , Williams, Thomas Albert
IPC分类号： H03K19/096 , H03K17/693
CPC分类号： H03K17/693 , H01L27/11803 , H03K19/096 , H03M7/005

16. 发明公开

EP0046197A1 FET convolved logic 失效
标题翻译：嵌套FET逻辑。
公开(公告)号：EP0046197A1
公开(公告)日：1982-02-24
申请号：EP81105494.9
申请日：1981-07-14
申请人： International Business Machines Corporation
发明人： Rosenbluth, William , Williams, Thomas Albert
IPC分类号： H03K19/096 , H03K17/693
CPC分类号： H03K17/693 , H01L27/11803 , H03K19/096 , H03M7/005
摘要： A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers.
The basic circuit element has an orthogonal arrangement of data transfer lines (w, x, y, z) and control signal lines (a, b, c, d). Active FETs (Q s to Q 8 ) have data inputs (L 1 to L 4 ) at their gates, their sources connected to ground and their drains connected to the data lines (w, x, y, z), respectively. Transfer devices (Q l to Q 4 ) have their source-drain path selectively connecting the data lines (w, x, y, z) to an output node (D 0 ), responding to control signals (G i to G 4 ), respectively. A depletion mode FET(Q o ) has its drain connected to a high level potential (V D ) and its source and gate connected to the output node (Do).

18. 发明授权

EP1873831B1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：EP1873831B1
公开(公告)日：2015-10-21
申请号：EP06122692.4
申请日：2006-10-20
申请人： Fujitsu Semiconductor Limited
发明人： Ema, Taiji c/o FUJITSU LIMITED, , Asano, Masayoshi c/o FUJITSU LIMITED, , Anezaki, Toru c/o FUJITSU LIMITED, , Ariyoshi, Junichi c/o FUJITSU LIMITED,
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/11803

19. 发明公开

EP2494599A4 SEMICONDUCTOR DEVICE 有权转让
公开(公告)号：EP2494599A4
公开(公告)日：2014-05-28
申请号：EP10826620
申请日：2010-10-15
申请人： SEMICONDUCTOR ENERGY LAB
发明人： YAMAZAKI SHUNPEI , KOYAMA JUN , KATO KIYOSHI
IPC分类号： H01L27/105 , G11C11/405 , G11C16/04 , H01L21/822 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L27/115 , H01L27/118 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1052 , G11C11/405 , G11C16/0433 , G11C2211/4016 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/11551 , H01L27/1156 , H01L27/11803 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/16 , H01L29/24 , H01L29/247 , H01L29/7833 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

20. 发明公开

EP1873831A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1873831A1
公开(公告)日：2008-01-02
申请号：EP06122692.4
申请日：2006-10-20
申请人： Fujitsu Ltd.
发明人： Ema, Taiji c/o FUJITSU LIMITED, , Ariyoshi, Junichi c/o FUJITSU LIMITED, , Anezaki, Toru c/o FUJITSU LIMITED, , Asano, Masayoshi c/o FUJITSU LIMITED,
IPC分类号： H01L27/092 , H01L21/762
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/11803
摘要： A semiconductor device includes: a p-type silicon substrate (20); a shallow n-well (34) formed in the silicon substrate (20); a shallow p-well (30) formed beside the shallow n-well (34) in the silicon substrate (20); and a deep n-well (28) which is formed beside the shallow p-well (30) in the silicon substrate (20), and which is deeper than the shallow p-well (30). In addition, a deep p-well (26), which is deeper than the shallow p-well (30), is formed between the shallow p-well (30) and the deep n-well (28) in the silicon substrate (20).
摘要翻译：一种半导体器件包括：p型硅衬底（20）; 在硅衬底（20）中形成的浅n阱（34）; 在硅衬底（20）中的浅n阱（34）旁边形成的浅p阱（30）; 以及形成在硅衬底（20）中的浅p阱（30）旁边并且比浅p阱（30）更深的深n阱（28）。此外，在硅衬底中的浅p阱（30）和深n阱（28）之间形成比浅p阱（30）更深的深p阱（26） 20）。

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