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11. 发明公开

EP1366570A1 IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH ULTRA THIN VERTICAL BODY TRANSISTORS 审中-公开
标题翻译： WITH ULTRA THIN竖直主体TRANSISTORS运算可编程逻辑阵列
公开(公告)号：EP1366570A1
公开(公告)日：2003-12-03
申请号：EP02724909.3
申请日：2002-02-06
申请人： MICRON TECHNOLOGY, INC.
发明人： FORBES, Leonard
IPC分类号： H03K19/177 , H01L25/00 , G06F7/38
CPC分类号： H01L27/11803 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/66825 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for in service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. At least one single crystalline ultra thin vertical floating gate transistor that is disposed adjacent each vertical pillar. The single crystalline vertical floating gate transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions. A vertical floating gate opposes the ultra thin single crystalline vertical body region.

12. 发明公开

EP0820100A3 Semiconductor device and manufacturing method for the same, basic cell library and manufacturing method for the same, and mask 失效
标题翻译：半导体装置及其制造方法，初级细胞库和它们的生产方法和掩模
公开(公告)号：EP0820100A3
公开(公告)日：2001-05-16
申请号：EP97111750.2
申请日：1997-07-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yamaguchi, Akira
IPC分类号： H01L27/02 , H01L27/118
CPC分类号： H01L27/11803 , G03F1/36 , H01L27/0207
摘要： There are provided a semiconductor device, basic cell library, a method for manufacturing a semi-conductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effect correction (OPC), reduce the CAD processing time, perform correction by the OPC for each cell, and reduce the product turn around time. A basic cell registered in the basic cell library has a dummy wiring pattern (4, 41, 42, 43, 44) previously formed on the peripheral portion thereof. With this structure, the distance between a polysilicon gate (3) used in a circuit and the polysilicon wiring of an adjacent dummy wiring pattern in the basic cell can be determined in the cell. As a result, variations in the poly-widths of all of the polysilicon gates in the basic cell due to the optical proximity effect can be estimated, and therefore, a correction value by the OPC on a mask for correcting the gate width based on the variation in the poly-width can be determined in the cell.

13. 发明授权

EP0376291B1 Semiconductor integrated circuit 失效
标题翻译：的半导体集成电路
公开(公告)号：EP0376291B1
公开(公告)日：1997-06-04
申请号：EP89124039.2
申请日：1989-12-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakata, Shigeharu Intellectual Property Division , Andoh, Kazumasa Intellectual Property Division
IPC分类号： H01L27/02 , H01L27/118 , H01L23/50 , H01L23/528
CPC分类号： H01L23/5286 , H01L23/528 , H01L27/11803 , H01L2924/0002 , H01L2924/00

14. 发明公开

EP0161734A3 Integrated circuit architecture and fabrication method therefor 失效
标题翻译：集成电路架构及其制造方法
公开(公告)号：EP0161734A3
公开(公告)日：1987-02-04
申请号：EP85300498
申请日：1985-01-25
申请人： Integrated Logic Systems, Inc.
发明人： Taylor, David Lee
IPC分类号： H01L27/02 , H01L21/82
CPC分类号： H01L27/11803 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A new ensemble of logic elements organized in an array and a method of forming the same is described wherein the architecture includes a main field of transistor elements formed on a substrate material. A group of load transistors and an array of logic gates are formed on the substrate and are located within the main field of transistors. At least one routing channel is provided in the main field, and an input/output structure is located on the substrate. A region of flip-flop elements, also located within the main field, may be provided. Preferably, a plurality of such groups, arrays and regions are formed in parallel strips extending across the main field, and a perpendicular bussing channel also extends across the field to divide the main field into component arrays. The logic gates may be configurable structures or dedicated inverters, and a plurality of input/output structures may be employed. The method includes the electrical interconnection of these elements into logic terms to form an integrated circuit.

15. 发明授权

EP0046197B1 FET convolved logic 失效
标题翻译： FET卷积逻辑
公开(公告)号：EP0046197B1
公开(公告)日：1984-05-16
申请号：EP81105494.9
申请日：1981-07-14
申请人： International Business Machines Corporation
发明人： Rosenbluth, William , Williams, Thomas Albert
IPC分类号： H03K19/096 , H03K17/693
CPC分类号： H03K17/693 , H01L27/11803 , H03K19/096 , H03M7/005

16. 发明公开

EP0046197A1 FET convolved logic 失效
标题翻译：嵌套FET逻辑。
公开(公告)号：EP0046197A1
公开(公告)日：1982-02-24
申请号：EP81105494.9
申请日：1981-07-14
申请人： International Business Machines Corporation
发明人： Rosenbluth, William , Williams, Thomas Albert
IPC分类号： H03K19/096 , H03K17/693
CPC分类号： H03K17/693 , H01L27/11803 , H03K19/096 , H03M7/005
摘要： A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers.
The basic circuit element has an orthogonal arrangement of data transfer lines (w, x, y, z) and control signal lines (a, b, c, d). Active FETs (Q s to Q 8 ) have data inputs (L 1 to L 4 ) at their gates, their sources connected to ground and their drains connected to the data lines (w, x, y, z), respectively. Transfer devices (Q l to Q 4 ) have their source-drain path selectively connecting the data lines (w, x, y, z) to an output node (D 0 ), responding to control signals (G i to G 4 ), respectively. A depletion mode FET(Q o ) has its drain connected to a high level potential (V D ) and its source and gate connected to the output node (Do).

17. 发明公开

EP3011593A1 METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY 有权
标题翻译： VERFAHREN UND VORRICHTUNGFÜREINEDIFFUSIONSVERBRÜCKTEZELLBIBLIOTHEK
公开(公告)号：EP3011593A1
公开(公告)日：2016-04-27
申请号：EP14740018.8
申请日：2014-06-17
申请人： QUALCOMM INCORPORATED
发明人： BOWERS, Benjamin John , HAYWARD, James W. , GOPAL, Charanya , BURDA, Gregory Christopher , BUCKI, Robert J. , GAN, Chock H. , NALLAPATI, Giridhar , YOUNGBLOOD, Matthew D. , FLEDERBACH, William R.
IPC分类号： H01L27/02 , G06F17/50 , H01L27/118
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H01L21/22 , H01L27/092 , H01L27/11521 , H01L27/11803 , H01L27/11807 , H01L29/66825 , Y02P90/265
摘要： A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.
摘要翻译：用于设计集成电路的单元库，该库包括连续扩散兼容（CDC）单元。 CDC单元包括电连接到电源轨的p掺杂扩散区，并且连接于CDC单元的左边缘到右边缘; 第一多晶硅栅极，其设置在p掺杂扩散区上方并电连接到p掺杂扩散区; 电连接到接地导轨并从左边缘到右边缘连续的n掺杂扩散区域; 第二多晶硅栅极，其设置在所述n掺杂扩散区域上方并电连接到所述n掺杂扩散区域; 设置在p掺杂和n掺杂扩散区上并靠近左边缘的左浮动多晶硅栅极; 以及设置在p掺杂和n掺杂扩散区上并靠近右边缘的右浮动多晶硅栅极。

18. 发明公开

EP2724373A2 TRANSISTOR AND ITS METHOD OF MANUFACTURE 有权转让
标题翻译： VERFAHREN ZU DESSEN HERSTELLUNG的TRANSISTOR
公开(公告)号：EP2724373A2
公开(公告)日：2014-04-30
申请号：EP12730616.5
申请日：2012-06-22
申请人： Pragmatic Printing Ltd
发明人： PRICE, Richard , WHITE, Scott
IPC分类号： H01L29/66 , H01L27/12
CPC分类号： H01L27/088 , G03F7/0002 , H01L21/0272 , H01L21/28008 , H01L21/283 , H01L21/31144 , H01L21/76895 , H01L21/823437 , H01L21/823475 , H01L23/528 , H01L27/11803 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L27/1292 , H01L29/66757 , H01L29/66969 , H01L29/78666 , H01L29/78675 , H01L29/7869 , H01L51/0541
摘要： A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.
摘要翻译：一种制造晶体管的方法，包括：提供衬底，由衬底支撑的半导体材料的区域和由半导体材料区域支撑的导电材料区域; 在所述区域上形成至少一层抗蚀剂材料，以在所述区域上形成抗蚀剂材料的覆盖层; 在抗蚀剂材料的覆盖物的表面上形成凹陷，所述凹陷在导电材料区域的第一部分上延伸，所述第一部分将导电区域的第二部分与导电区域的第三部分分开; 去除位于所述凹陷下方的抗蚀剂材料，以形成通过所述覆盖物的窗口，暴露所述导电区域的所述第一部分; 去除所述第一部分以暴露所述半导体材料区域的连接部分，所述连接部分将所述第二部分连接到所述导电区域的第三部分; 在半导体材料的区域的暴露部分上形成介电材料层; 以及沉积导电材料以在所述介电材料层上形成导电材料层，所述介电材料层将所述导电材料层与所述导电区域的第二和第三部分电隔离。

19. 发明公开

EP2568506A1 Tunnel transistor, logical gate comprising the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor 审中-公开
标题翻译：隧道晶体管，含晶体管逻辑门，所述逻辑门使用的静态随机存取存储器设备以及用于制造这种隧道晶体管的方法
公开(公告)号：EP2568506A1
公开(公告)日：2013-03-13
申请号：EP11180814.3
申请日：2011-09-09
申请人： IMEC , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Heyns, Marc , Huyghebaert, Cedric , Verhulst, Anne S. , Leonelli, Daniele , Rooyackers, Rita , Dehaene, Wim
IPC分类号： H01L29/739 , H01L21/8244 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7391 , B82Y10/00 , H01L27/11 , H01L27/11803 , H01L29/0657 , H01L29/66977 , H01L29/7831 , H01L29/78648 , H01L29/78684
摘要： A tunnel transistor (1) comprising a drain (2), a source (4) and a first gate (6) and a second gate (10) for controlling current between the drain (2) and the source (4), wherein the first sides (9,13) of respectively the first and the second gate dielectric material (7,11) are positioned substantially along and substantially contact respectively a first and a second semiconductor part (14,15).
摘要翻译：甲隧道晶体管（1），包括漏（2），源极（4）和第一栅极（6）和用于控制所述漏极之间的电流的第二栅极（10）（2）和所述源（4），worin的第一侧面分别与第一和第二栅极介电材料（7.11）的（9,13）沿着基本上位于与分别基本上接触的第一和第二半导体部（14,15）。

20. 发明公开

EP2030206A2 A METHOD FOR PROGRAMMING AND ERASING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZE BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS 有权
标题翻译：方法用于编程和取消ARRAY NMOS EEPROM细胞MINIMIZE位扰动，将电源开关要求存储器阵列及支持电路的
公开(公告)号：EP2030206A2
公开(公告)日：2009-03-04
申请号：EP07797769.2
申请日：2007-05-25
申请人： Microchip Technology Incorporated
发明人： HEWITT, Kent , GERBER, Donald , SHIELDS, Jeffrey A.
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

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