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    • 13. 发明公开
    • CHIP SCALE PACKAGE LIGHT EMITTING DIODE
    • EP4297105A2
    • 2023-12-27
    • EP23208095.2
    • 2018-12-10
    • Seoul Viosys Co., Ltd.
    • KIM, Jong KyuKANG, Min WooOH, Se HeeLIM, Hyoung Jin
    • H01L33/40
    • A light emitting diode module, comprising a printed circuit board (1023), and a light emitting diode (1021) disposed on the substrate, the light emitting diode including a substrate (21), a first conductivity type semiconductor layer (23), a mesa (M) disposed on the first conductivity type semiconductor layer (23), and including an active layer (25) and a second conductivity type semiconductor layer (27), an ohmic contact layer (28) disposed on the mesa (M) and electrically connected to the second conductivity type semiconductor layer (27), a lower insulation layer (33) covering the mesa (M), and including at least one first opening (33a1) exposing the first conductivity type semiconductor layer (23) and a second opening (33a2), a first pad metal layer (35a) disposed on the lower insulation layer (33), and electrically connected to the first conductivity type semiconductor layer (23) through the at least one first opening (33a1), a second pad metal layer (35b) disposed on the lower insulation layer (33), and electrically connected to the ohmic contact layer (28) through the second opening (33a2), a upper insulation layer (37) covering the first and second pad metal layers (35a, 35b) and including first opening (37a) exposing the first pad metal layer (35a) and a second opening (37b) exposing the second pad metal layer (35b), a first bump pad (39a) disposed on the upper insulation (37), and electrically connected to the first pad metal layer (35a) through the first opening (37a) of the upper insulation layer(37), and a second bump pad (39b) disposed on the upper insulation (37), and electrically connected to the second pad metal layer (35b) through the second opening (37b) of the upper insulation layer(37), wherein the first pad metal layer (35a) includes a protrusion having an outer contact portion (35a1) that contacts the first conductivity type semiconductor layer (23) near the edge of the substrate (21), and wherein the first pad metal layer (35a) includes a region that has a wide width and a region that has a narrow width extending from thereof.