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11. 发明公开

EP3050092A1 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 审中-公开
标题翻译：之间。通过组合选择性，符合外延在硅衬底EYED FOR CMOS硅-FREE装置的各层
公开(公告)号：EP3050092A1
公开(公告)日：2016-08-03
申请号：EP13894917.7
申请日：2013-09-27
申请人： Intel Corporation
发明人： GOEL, Niti , CHAU, Robert S. , KAVALIEROS, Jack T. , CHU-KUNG, Benjamin , METZ, Matthew V. , MUKHERJEE, Niloy , ZELICK, Nancy M. , DEWEY, Gilbert , RACHMADY, Willy , RADOSAVLJEVIC, Marko , LE, Van H. , PILLARISETTY, Ravi , DASGUPTA, Sansaptak
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

12. 发明公开

EP3042390A1 METHODS AND STRUCTURES TO PREVENT SIDEWALL DEFECTS DURING SELECTIVE EPITAXY 审中-公开
标题翻译：方法和结构断开的过程中选择性外延防偏WALL
公开(公告)号：EP3042390A1
公开(公告)日：2016-07-13
申请号：EP13892844.5
申请日：2013-09-04
申请人： Intel Corporation , Goel, Niti , Pathi, Pragyansri , Dasgupta, Sansaptak , Powers, James M. , Chu-kung, Benjamin , Chau, Robert S.
发明人： MUKHERJEE, Niloy , GOEL, Niti , GARDNER, Sanaz K. , PATHI, Pragyansri , METZ, Matthew V. , DASGUPTA, Sansaptak , SUNG, Seung Hoon , POWERS, James M. , DEWEY, Gilbert , CHU-KUNG, Benjamin , KAVALIEROS, Jack T. , CHAU, Robert S.
IPC分类号： H01L21/20
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/02516 , H01L21/02532 , H01L21/02538 , H01L21/02609 , H01L21/02636 , H01L21/02639 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/7848
摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
摘要翻译：设置的沟槽（与用于形成沟槽的过程）并减少或防止在类型III-V族或锗（Ge）材料（E. G.，“缓冲”材料）的选择性外延生长晶形缺陷从基片材料的顶表面上。缺陷可能是由与侧壁氧化物沟槽侧壁选择性外延生长的碰撞。搜索沟槽包括（I）在以40度和70度之间的角度具有倾斜的沟槽侧壁：相对于表面的基材;（E. G，如55度）。和/或（2）具有组合沟槽上沟槽上方和周围的下部沟槽的开口（例如，下沟槽可以具有倾斜侧壁，短的垂直壁，或高的竖直壁）。这些沟槽减小或防止在外延侧壁生长缺陷，其中生长触及或生长针对它在生长在沟槽的垂直侧壁。

13. 发明公开

EP3161854A1 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：法制造密度泛函单元的排列
公开(公告)号：EP3161854A1
公开(公告)日：2017-05-03
申请号：EP14896073.5
申请日：2014-06-25
申请人： Intel Corporation
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：技术是圆盘游离缺失用于形成使用下一代光刻（NGL）的过程，：例如电子束直写（EBDW）和极紫外光刻（EUVL），以形成所述阵列中的单元的边界功能性细胞的压实的阵列。细胞的压实的阵列可用于现场可编程门阵列（FPGA）与逻辑单元配置的结构，静态随机存取存储器（SRAM）与位单元，或其它存储器或具有基于细胞的结构逻辑器件配置结构。的技术可以用来获得在10面积％至50％的降低，例如，对于功能单元的阵列，因为NGL工艺允许更高的精度和对小区边界更靠近切割，相比于传统的193nm光刻，此外，使用NGL工艺，以形成用于细胞因此可以减少光刻引起的变化，否则也将存在与常规的193nm的光刻法的边界。

14. 发明公开

EP2901490A1 SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING PARASITIC LEAKAGE BARRIER LAYER 有权
标题翻译：与锗活动层半导体部件包括架空寄生泄漏阻隔件
公开(公告)号：EP2901490A1
公开(公告)日：2015-08-05
申请号：EP13842724.0
申请日：2013-06-24
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , GOEL, Niti , THEN, Han Wui , LE, Van H. , RACHMADY, Willy , RADOSAVLJEVIC, Marko , DEWEY, Gilbert , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/28255 , H01L29/0673 , H01L29/1054 , H01L29/1079 , H01L29/1083 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/785 , H01L29/78696
摘要： Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

15. 发明公开

EP2901489A1 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING 有权转让
标题翻译：围堵缺陷的方法可在无硅器件的生产
公开(公告)号：EP2901489A1
公开(公告)日：2015-08-05
申请号：EP13842603.6
申请日：2013-06-24
申请人： Intel Corporation
发明人： GOEL, Niti , PILLARISETTY, Ravi , MUKHERJEE, Niloy , CHAU, Robert S. , RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko , CHU-KUNG, Benjamin , DEWEY, Gilbert , SUNG, Seung Hoon
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/0245 , H01L21/02538 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/1054 , H01L29/1083 , H01L29/267 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

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