专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明公开

EP2901489A1 METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING 有权转让
标题翻译：围堵缺陷的方法可在无硅器件的生产
公开(公告)号：EP2901489A1
公开(公告)日：2015-08-05
申请号：EP13842603.6
申请日：2013-06-24
申请人： Intel Corporation
发明人： GOEL, Niti , PILLARISETTY, Ravi , MUKHERJEE, Niloy , CHAU, Robert S. , RACHMADY, Willy , METZ, Matthew V. , LE, Van H. , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko , CHU-KUNG, Benjamin , DEWEY, Gilbert , SUNG, Seung Hoon
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/0245 , H01L21/02538 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/1054 , H01L29/1083 , H01L29/267 , H01L29/42392 , H01L29/66469 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78696
摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

12. 发明公开

EP3161840A1 TECHNIQUES FOR FORMING INTEGRATED PASSIVE DEVICES 审中-公开
标题翻译：形成集成无源器件的技术
公开(公告)号：EP3161840A1
公开(公告)日：2017-05-03
申请号：EP14895620.4
申请日：2014-06-25
申请人： Intel Corporation
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ROY, Anshumali , YIP, Joseph, C.
IPC分类号： H01F17/00 , H01G4/32 , H01F41/04
CPC分类号： H01L23/66 , G03F7/2059 , H01F17/0006 , H01F41/042 , H01G4/012 , H01G4/40 , H01L28/10 , H01L28/60 , H01L2223/6672
摘要： Techniques are disclosed for forming integrated passive devices, such as inductors and capacitors, using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL). The techniques can be used to form various different integrated passive devices, such as inductors (e.g., spiral inductors) and capacitors (e.g., metal finger capacitors), having higher density, precision, and quality factor (Q) values than if such devices were formed using 193 nm photolithography. The high Q and dense passive devices formed can be used in radio frequency (RF) and analog circuits to boost the performance of such circuits. The increased precision may be realized based on an improvement in, for example, line edge roughness (LER), achievable resolution/critical dimensions, sharpness of corners, and/or density of the formed structures.
摘要翻译：公开了使用诸如电子束直写（EBDW）和极紫外光刻（EUVL）的下一代光刻（NGL）工艺来形成诸如电感器和电容器的集成无源器件的技术。这些技术可用于形成各种不同的集成无源器件，例如电感器（例如螺旋电感器）和电容器（例如金属指状电容器），其密度，精度和品质因数（Q）值高于如果这样的器件是使用193纳米光刻法形成。所形成的高Q和密集无源器件可用于射频（RF）和模拟电路，以提高此类电路的性能。可以基于例如线边缘粗糙度（LER），可实现的分辨率/关键尺寸，拐角的锐度和/或所形成的结构的密度的改进来实现提高的精确度。

13. 发明授权

EP2382667B1 TUNNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME 有权
标题翻译：隧穿晶体管和场效应用于生产
公开(公告)号：EP2382667B1
公开(公告)日：2017-01-25
申请号：EP09836962.2
申请日：2009-12-17
申请人： Intel Corporation
发明人： GOEL, Niti , TSAI, Wilman , KAVALIEROS, Jack
IPC分类号： H01L29/739
CPC分类号： H01L29/7391 , H01L29/205 , H01L29/66356

14. 发明公开

EP3050092A1 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 审中-公开
标题翻译：之间。通过组合选择性，符合外延在硅衬底EYED FOR CMOS硅-FREE装置的各层
公开(公告)号：EP3050092A1
公开(公告)日：2016-08-03
申请号：EP13894917.7
申请日：2013-09-27
申请人： Intel Corporation
发明人： GOEL, Niti , CHAU, Robert S. , KAVALIEROS, Jack T. , CHU-KUNG, Benjamin , METZ, Matthew V. , MUKHERJEE, Niloy , ZELICK, Nancy M. , DEWEY, Gilbert , RACHMADY, Willy , RADOSAVLJEVIC, Marko , LE, Van H. , PILLARISETTY, Ravi , DASGUPTA, Sansaptak
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

15. 发明公开

EP3042390A1 METHODS AND STRUCTURES TO PREVENT SIDEWALL DEFECTS DURING SELECTIVE EPITAXY 审中-公开
标题翻译：方法和结构断开的过程中选择性外延防偏WALL
公开(公告)号：EP3042390A1
公开(公告)日：2016-07-13
申请号：EP13892844.5
申请日：2013-09-04
申请人： Intel Corporation , Goel, Niti , Pathi, Pragyansri , Dasgupta, Sansaptak , Powers, James M. , Chu-kung, Benjamin , Chau, Robert S.
发明人： MUKHERJEE, Niloy , GOEL, Niti , GARDNER, Sanaz K. , PATHI, Pragyansri , METZ, Matthew V. , DASGUPTA, Sansaptak , SUNG, Seung Hoon , POWERS, James M. , DEWEY, Gilbert , CHU-KUNG, Benjamin , KAVALIEROS, Jack T. , CHAU, Robert S.
IPC分类号： H01L21/20
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/02516 , H01L21/02532 , H01L21/02538 , H01L21/02609 , H01L21/02636 , H01L21/02639 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/8258 , H01L27/0924 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/7848
摘要： Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
摘要翻译：设置的沟槽（与用于形成沟槽的过程）并减少或防止在类型III-V族或锗（Ge）材料（E. G.，“缓冲”材料）的选择性外延生长晶形缺陷从基片材料的顶表面上。缺陷可能是由与侧壁氧化物沟槽侧壁选择性外延生长的碰撞。搜索沟槽包括（I）在以40度和70度之间的角度具有倾斜的沟槽侧壁：相对于表面的基材;（E. G，如55度）。和/或（2）具有组合沟槽上沟槽上方和周围的下部沟槽的开口（例如，下沟槽可以具有倾斜侧壁，短的垂直壁，或高的竖直壁）。这些沟槽减小或防止在外延侧壁生长缺陷，其中生长触及或生长针对它在生长在沟槽的垂直侧壁。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式