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91. 发明公开

EP1953916A1 LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD 审中-公开
标题翻译： LOGIKBLOCK-STEUERSYSTEM UND LOGIKBLOCK-STEUERVERFAHREN
公开(公告)号：EP1953916A1
公开(公告)日：2008-08-06
申请号：EP06832685.9
申请日：2006-11-15
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： ICHINOMIYA, Takahiro c/o Matsushita Electric Industrial Co., Ltd.
IPC分类号： H03K19/173 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/15
CPC分类号： H03K19/1774 , H03K19/17784
摘要： The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of alogicblock, a gated clock technique, apower-off technique, or the like is used.
摘要翻译：获得在可编程逻辑单元中执行目标处理时可以停止的块的数量，并且计算包括在可编程逻辑单元中的多个逻辑块中的每一个的停止率。以停止率的升序从多个逻辑块中选择与可停止的块相同数量的逻辑块，所选择的逻辑块被确定为其操作将被停止的逻辑块，并且操作是停止。作为停止alogicblock的操作的技术，使用门控时钟技术，apower-off技术等。

92. 发明授权

EP1325519B1 Semiconductor apparatus with improved ESD withstanding voltage 有权
标题翻译：具有改进的ESD电阻电压半导体器件
公开(公告)号：EP1325519B1
公开(公告)日：2008-06-11
申请号：EP02747664.7
申请日：2002-07-12
申请人： Ricoh Company, Ltd.
发明人： OKAZAKI, Miho
IPC分类号： H01L27/04 , H01L21/82 , H01L27/088 , H01L27/02
CPC分类号： H01L27/0266 , H01L27/0251 , H01L2924/0002 , H01L2924/00

93. 发明公开

EP1396031A4 DMOS WITH ZENER DIODE FOR ESD PROTECTION 审中-公开
标题翻译：齐纳管DMOS用于ESD保护
公开(公告)号：EP1396031A4
公开(公告)日：2008-04-09
申请号：EP02751992
申请日：2002-05-22
申请人： GEN SEMICONDUCTOR INC
发明人： HSHIEH FWU-IUAN , SO KOON CHONG
IPC分类号： H01L21/336 , H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/49 , H01L29/78 , H01L29/866
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/7808 , H01L2924/0002 , H01L2924/00
摘要： A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.

94. 发明公开

EP1600530A4 (001)-ORIENTATED PEROVSKITE FILM FORMATION METHOD AND DEVICE HAVING PEROVSKITE FILM 有权
标题翻译：用于生产（001）取向PEROWSKITFILMS及其装置PEROWSKITFILM
公开(公告)号：EP1600530A4
公开(公告)日：2008-03-19
申请号：EP03816159
申请日：2003-03-04
申请人： FUJITSU LTD
发明人： KONDO MASAO , KURIHARA KAZUAKI
IPC分类号： C30B23/02 , H01G4/06 , H01L21/02 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L41/09 , H01L41/187 , H01L41/22 , H01L41/316 , H01L41/319 , H01L41/39 , H03H9/02 , C30B29/22 , H01L27/10 , H01L41/08 , H01L41/18 , H03H3/08
CPC分类号： C30B23/02 , C30B29/22 , C30B29/225 , H01L21/02197 , H01L21/02266 , H01L21/02304 , H01L21/02337 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L28/55 , H01L28/65 , H01L29/516 , H01L41/0478 , H01L41/319 , H03H9/02574
摘要： The present invention generally relates to a device having a ferroelectric film, and particularly, to a semiconductor device having a ferroelectric film being epitaxially grown on a silicon substrate. A capacitance device of the present invention includes a substrate having a (111) orientation, an epitaxial film formed on the substrate and having a perovskite structure and a (001) orientation, and an electrode formed on the epitaxial film. A method of forming an epitaxial film having a perovskite structure according to the present invention includes a step of epitaxially growing, on a substrate having a (111) orientation, a metal oxide film of a rock salt structure and having a (001) orientation, and a step of further epitaxially growing, on the metal oxide film, a metal oxide film of a perovskite structure and having a (001) orientation. According to the present invention, it is possible to fabricate devices having various functions, such as a ferroelectric random access memory, a SAW filter, or a ferroelectric actuator.

95. 发明公开

EP1886377A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：EP1886377A1
公开(公告)日：2008-02-13
申请号：EP06766429.2
申请日：2006-05-26
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： AOKI, Tomoyuki , DAIRIKI, Koji , GOTO, Yuugo
IPC分类号： H01Q1/24 , G06K19/07 , G06K19/077 , H01L21/02 , H01L21/20 , H01L21/768 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792 , H01Q7/00
CPC分类号： H01L27/13 , G06K19/07749 , H01L21/6835 , H01L23/5227 , H01L23/552 , H01L23/576 , H01L23/585 , H01L27/105 , H01L27/11509 , H01L27/11526 , H01L27/11546 , H01L27/1203 , H01L27/124 , H01L27/1266 , H01L29/78618 , H01L2221/6835 , H01L2221/68368 , H01L2924/0002 , H01L2924/12044 , H01L2924/30105 , H01Q1/2208 , H01L2924/00
摘要： It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device of the invention includes an element group including a plurality of transistors over a substrate; a first conductive film functioning as an antenna over the element group; a second conductive film surrounding the first conductive film; an insulating film covering the first and second end portions; and a third conductive film over the insulating film. The first conductive film is provided in the shape of a coil, and each end portion of the first conductive film is connected to the element group. First and second end portions of the second conductive film are not connected to each other.
摘要翻译：本发明的一个目的是提供一种半导体器件，即使当在商业产品上安装可以无接触地交换数据的半导体器件时，该半导体器件也可以保护消费者或商业产品的持有者的隐私并根据使用来控制通信范围。本发明的半导体器件包括在衬底上包括多个晶体管的元件组; 用作元件组上方的天线的第一导电膜; 围绕第一导电膜的第二导电膜; 覆盖第一和第二端部的绝缘膜; 以及绝缘膜上的第三导电膜。第一导电膜被设置成线圈状，并且第一导电膜的每个端部连接到元件组。第二导电膜的第一和第二端部不彼此连接。

96. 发明公开

EP1858073A1 SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD, AND SIGNAL TRANSMISSION CIRCUIT 审中-公开
标题翻译：半导体集成电路，控制方法为一体的综合半导体电路和信号传输电路
公开(公告)号：EP1858073A1
公开(公告)日：2007-11-21
申请号：EP06714019.4
申请日：2006-02-17
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： ITO, Minoru c/o Matsushita Elec:Indus:Co.,Ltd , SHIMURA, Hidekichi c/o Matsushita Elec:Indus:Co.,Ltd
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/08 , H01L29/786 , H03K17/30 , H03K17/687 , H03K19/0175 , H03K19/0185 , H03K19/094 , H03K19/0948
CPC分类号： H01L27/1203 , H03K19/0016
摘要： A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks (400a to 400n) are composed of MIS transistors fabricated on an SOI structure silicon substrate and have at least one potential set including a high-potential side potential, a low-potential side potential, a substrate potential of a P-channel MIS transistor, and a substrate potential of an N-channel MIS transistor. Power supply wirings supply voltages to the potentials included in the potential set, a controller (200) determines the values of the voltages induced in the power supply wirings and instructs a power supply control IC (300) to generate the voltages of the determined values, and the power supply control IC (300) generates the voltages induced in the power supply wirings according to the instruction of the controller (200).
摘要翻译：一种半导体集成电路，半导体集成电路的控制方法以及信号传输电路实现的半导体集成电路和减少功率消耗的性能的优化。在该半导体集成电路，半导体集成电路的控制方法以及信号传输电路，功能电路块（400A至400N）由在硅衬底上制造在SOI结构的MIS晶体管和具有至少一个潜在集，包括一个高电位侧电位，低电位侧电位，P沟道MIS晶体管的潜在底物，和N沟道MIS晶体管的衬底电位。电源布线供给电压的电势包括在潜在的集合，一个控制器（200）确定的地雷在电源布线引起的，并指示电源控制IC（300），以产生确定性开采值的电压的电压的值，和电源控制IC（300）的基因率电源布线gemäß感应到控制器（200）的指令的电压。

97. 发明公开

EP1851802A1 CIRCUIT FOR PROTECTING ELECTRICAL AND/OR ELECTRONIC SYSTEM BY USING ABRUPT METAL-INSULATOR TRANSITION DEVICE AND ELECTRICAL AND/OR ELECTRONIC SYSTEM COMPRISING THE CIRCUIT 审中-公开
标题翻译：电路保护电气和/或电子系统通过使用具有突变金属 - 绝缘体转变电路和全面的电气和/或电子系统中的设备
公开(公告)号：EP1851802A1
公开(公告)日：2007-11-07
申请号：EP06715993.9
申请日：2006-02-17
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： KIM, Hyun-Tak , KANG, Kwang-Yong , CHAE, Byung-Gyu , KIM, Bong-Jun , YUN, Sun-Jin , LEE, Yong-Wook , KIM, Gyung-Ock , YOUN, Doo-Hyeb , LIM, Jung-Wook
IPC分类号： H01L27/04 , H01L29/772
CPC分类号： H01L49/003 , H01L27/0248
摘要： Provided are an electrical and/or electronic system protecting circuit using an abrupt metal-insulator transition (MIT) device which can effectively remove high-frequency noise with a voltage greater than a rated standard voltage received via a power line or a signal line of an electrical and/or electronic system, and the electrical and/or electronic system including the electrical and/or electronic system protecting circuit. The abrupt MIT device of the electrical and/or electronic system protecting circuit abrupt is connected in parallel to the electrical and/or electronic system to be protected from the noise. The electrical and/or electronic system protecting circuit bypasses toward the abrupt MIT device most of the noise current generated when the voltage greater than the rated standard voltage is applied, thereby protecting the electrical and/or electronic system.

98. 发明公开

EP1391991A4 INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：集成电路部件
公开(公告)号：EP1391991A4
公开(公告)日：2007-10-24
申请号：EP02728137
申请日：2002-05-24
申请人： IP FLEX INC
发明人： IKEDA KENJI , SHIMURA HIROSHI , SATO TOMOYOSHI
IPC分类号： G06F15/78 , G06F17/50 , H03K19/173 , G06F15/16 , H01L21/82 , H01L27/04
CPC分类号： G06F17/5045 , G06F15/7867
摘要： An integrated circuit device comprises a processing section including arithmetic units arranged in a matrix, a first group of lines extending in a first direction of the matrix and adapted for transmitting input data inputted to the arithmetic units, a second group of lines extending in a second direction of the matrix and adapted for transmitting output data outputted from the arithmetic units, switching units arranged at intersections of the lines of the first and second groups and adapted for selecting a line out of the first group and a line out of the second group to interconnect them. The arithmetic units include ones suited to specific processings and having different data paths. In at least a part of the data processing section, there is an array of arithmetic units of the same type extending in the first or second direction. Since the combination of the arithmetic units of the integrated circuit device can be changed, the function can be dynamically changed. Further the integrated circuit device is constituted of arithmetic units having different data paths suitable to specific processings and consequently is compact and economical.

99. 发明公开

EP1357598A4 SEMICONDUCTOR DEVICE AND PORTABLE ELECTRONIC DEVICE 审中-公开
标题翻译：半导体部件和便携式电子设备
公开(公告)号：EP1357598A4
公开(公告)日：2007-10-10
申请号：EP01271852
申请日：2001-12-21
申请人： SHARP KK
发明人： SHIBATA AKIHIDE , IWATA HIROSHI , KAKIMOTO SEIZO
IPC分类号： H01L21/822 , H01L21/761 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/08 , H01L21/76 , H01L21/8234 , H01L27/088
CPC分类号： H01L27/0928 , H01L21/761 , H01L21/823878 , H01L21/823892
摘要： A semiconductor device comprising a DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions (12) are formed in one P-type semiconductor substrate (11). The N-type deep well regions (12, 12) are electrically isolated by the P-type semiconductor substrate (11). Over the N-type deep well regions (12), a P-type deep well region (13) and a P-type shallow well region (15) are formed to fabricate an N-type substrate variable-bias transistor (26). Over the N-type deep well region (12), an N-type shallow well region (14) is formed to fabricate a P-type substrate variable-bias transistor (25). Further a P-type DTMOS (28) and an N-type DTMOD (27) are fabricated.

100. 发明公开

EP1837668A1 SEMICONDUCTOR DEVICE, TEST APPARATUS AND MEASURING METHOD 审中-公开
标题翻译： HALBLEITERBAUEMENT，TESTVORRICHTUNG UND MESSVERFAHREN
公开(公告)号：EP1837668A1
公开(公告)日：2007-09-26
申请号：EP05809363.4
申请日：2005-11-24
申请人： ADVANTEST CORPORATION
发明人： YAMAZAKI, Makoto, ADVANTEST CORPORATION , MATSUMURA, Hidenobu, ADVANTEST CORPORATION , FURUKAWA, Yasuo, ADVANTEST CORP.
IPC分类号： G01R31/317 , H01L27/04
CPC分类号： G01R31/3016 , G01R31/31717
摘要： A semiconductor device for measuring delay time of a wiring under test provided therein is provided, in which the semiconductor device includes: a loop path on which the wiring under test is provided; a delay element for delaying an input signal by a predetermined time; a delay selecting unit for determining whether or not the delay element is connected on the loop path; a loop delay measuring unit for measuring delay time of the loop path; a first gate delay estimating unit for estimating delay time of the delay element by subtracting delay time of the loop path in case the delay element is not connected on the loop path from delay time of the loop path in case the delay element is connected on the loop path; a second gate delay estimating unit for estimating delay time of a logic circuit connected on the loop path on the basis of the delay time of the delay element; and a wiring delay estimating unit for estimating delay time of the wiring under test.
摘要翻译：提供一种半导体装置，用于测量在其中提供的被测配线的延迟时间，其中半导体器件包括：设置有被测线路的环路; 用于将输入信号延迟预定时间的延迟元件; 延迟选择单元，用于确定所述延迟元件是否连接在所述环路径上; 环路延迟测量单元，用于测量环路径的延迟时间; 第一门延迟估计单元，用于通过在所述延迟元件连接到所述延迟元件的情况下从所述环路径的延迟时间在所述环路径上未连接所述延迟元件的情况下减去所述环路径的延迟时间来估计所述延迟元件的延迟时间循环路径第二门延迟估计单元，用于基于延迟元件的延迟时间估计连接在环路上的逻辑电路的延迟时间; 以及布线延迟估计单元，用于估计被测线路的延迟时间。

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