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91. 发明公开

EP1852909A1 Process for integrating a non-volatile memory cell into a HV CMOS process 审中-公开
标题翻译： Verfahren zur集成einernichtflüchtigenSpeicherzelle在einen HV CMOS Prozess
公开(公告)号：EP1852909A1
公开(公告)日：2007-11-07
申请号：EP06009365.5
申请日：2006-05-05
申请人： austriamicrosystems AG
发明人： Leisenberger, Friedrich Peter , Park, Jong Mun
IPC分类号： H01L21/8247 , H01L27/105 , H01L29/423 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546
摘要： A process is given which can integrate the production of an EEPROM cell into a CMOS process without deteriorating the oxide quality of the CMOS gate oxides. It proposed the EEPROM floating gate (PS1) and the covering intermediate dielectric (10) is formed first and protected with a silicon nitride layer (SN) before forming the gate oxide areas of the CMOS structure.
摘要翻译：给出了可以将EEPROM单元的生产集成到CMOS工艺中而不劣化CMOS栅极氧化物的氧化物质的过程。提出了EEPROM浮栅（PS1），首先形成覆盖中间电介质（10），并在形成CMOS结构的栅极氧化物区域之前用氮化硅层（SN）进行保护。

92. 发明公开

EP1840947A2 Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：EP1840947A2
公开(公告)日：2007-10-03
申请号：EP07005504.1
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/105 , H01L27/12 , H01L29/788 , G11C11/56 , G11C16/04 , H01L29/423 , H01L29/786 , H01L27/02
CPC分类号： H01L27/1237 , G11C16/0416 , G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11546 , H01L27/1214 , H01L29/513 , H01L29/66825 , H01L29/7883 , H01L29/7885
摘要： It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer (14) including a channel forming region (15) between a pair of impurity regions (18) which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer (16), a floating gate electrode (20), a second insulating layer (22), and a control gate electrode (24) are provided. The floating gate (20) has at least a two-layer structure, and a first layer (20a) being in contact with the first insulating layer (16) preferably has a band gap smaller than that of the semiconductor layer (14). The stability of the first layer (20a) is improved by formation of a second layer (20b) of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
The first layer (20a) can comprise SiGe.
摘要翻译：目的在于提供一种具有优异的写入性能和电荷保持性能的非易失性半导体存储器件。提供在彼此分开形成的一对杂质区域（18）之间包括沟道形成区域（15）的半导体层（14）。在其上层部分中，提供第一绝缘层（16），浮置栅电极（20），第二绝缘层（22）和控制栅电极（24）。浮置栅极（20）至少具有双层结构，与第一绝缘层（16）接触的第一层（20a）的带隙优选小于半导体层（14）的带隙。通过使用金属，合金或金属化合物材料形成浮置栅电极的第二层（20b），第一层（20a）的稳定性得到改善。浮栅电极的这种结构可以提高写入时的载流子的注入性和电荷保持性。第一层（20a）可以包含SiGe。

93. 发明公开

EP1829108A1 MULTI-THICKNESS DIELECTRIC FOR SEMICONDUCTOR MEMORY 审中-公开
标题翻译：电介质与半导体存储器多厚
公开(公告)号：EP1829108A1
公开(公告)日：2007-09-05
申请号：EP05854664.9
申请日：2005-12-15
申请人： SanDisk Corporation
发明人： HIGASHITANI, Masaaki , PHAM, Tuan
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.

94. 发明公开

EP1816675A1 Manufacturing process of spacers for high-voltage transistors in an EEPROM device 审中-公开
标题翻译：在einer EEPROM-Vorrichtung的Herstellungsverfahren von SpacernfürHochspannungstransistoren
公开(公告)号：EP1816675A1
公开(公告)日：2007-08-08
申请号：EP06425059.0
申请日：2006-02-03
申请人： STMicroelectronics S.r.l.
发明人： Costantini, Sonia , Pavan, Alessia , Servalli, Giorgio
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534 , H01L27/11539 , H01L27/11543 , H01L27/11546
摘要： Process for manufacturing a non volatile memory electronic device (2) integrated on a semiconductor substrate (1) which comprises a matrix of non volatile memory cells (4), said memory cells (4) organised in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors (3), comprising the steps of:
- forming, by means of a photo-lithographic process which provides the use of a first photo-lithographic mask, gate electrodes (12) of the high voltage transistors (3) projecting from a first portion (A) of the semiconductor substrate (1).
- forming first spacers (15) on the side walls of the gate electrodes (12) of said high voltage transistors (3) of a first length (L1),
- forming, by means of a photo-lithographic process which provides the use of a second photo lithographic mask which covers said high voltage transistors (3), gate electrodes (16) of said memory cells (4) projecting from a second portion (B) of said semiconductor substrate (1), each of said gate electrodes (16) of memory cells (4) comprising a floating gate electrode (FG) and a control gate electrode (CG)
摘要翻译：一种集成在半导体衬底（1）上的非易失性存储器件（2）的制造方法，该半导体衬底（1）包括非易失性存储器单元（4）的矩阵，所述存储单元（4）被组织成行，称为字线和列，所谓的位线和包括高压晶体管（3）的相关电路，包括以下步骤： - 通过提供使用第一光刻掩模的光刻工艺，形成所述第一光刻掩模的栅电极（12）从半导体衬底（1）的第一部分（A）伸出的高电压晶体管（3）。 - 在第一长度（L1）的所述高压晶体管（3）的栅极（12）的侧壁上形成第一间隔物（15）， - 通过光刻工艺形成，所述光刻工艺提供使用覆盖所述高压晶体管（3）的第二光刻掩模，从所述半导体衬底（1）的第二部分（B）突出的所述存储单元（4）的栅电极（16），每个所述栅电极）包括浮栅电极（FG）和控制栅电极（CG）的存储单元（4）

95. 发明公开

EP1703520A1 Semiconductor integrated circuit and nonvolatile memory element 有权
标题翻译：半导体集成电路和非易失性存储器元件
公开(公告)号：EP1703520A1
公开(公告)日：2006-09-20
申请号：EP06011387.5
申请日：2000-01-19
申请人： HITACHI, LTD.
发明人： Syukuri, Syoji, c/o Hitachi, Ltd. , Komori, Kazuhiro, c/o Hitachi, Ltd. , Okuyama, Kousuke, c/o Hitachi, Ltd. , Kubota, Katsuhiko, c/o Hitachi, Ltd.
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.
摘要翻译：基于包括差分形式的一对非易失性存储元件的存储单元的信息保持能力得到改善。构成闪速存储器的非易失性存储元件（130）被构造成通过利用晶体管的栅氧化膜（GT2）和栅电极（GT2）分别形成其隧道氧化膜（G03）和浮栅电极（FGT）用于形成在与元件（130）相同的半导体衬底上的电路。存储器单元以2单元/ 1位方案构造，其中一对非易失性存储器元件可以分别连接到一对互补数据线，并且对于非易失性存储器元件设置彼此不同的阈值电压状态以差分读出数据。

96. 发明公开

EP1687844A2 METHOD OF FORMING A LOW VOLTAGE GATE OXIDE LAYER AND TUNNEL OXIDE LAYER IN AN EEPROM CELL 审中-公开
标题翻译：方法中在EEPROM单元中的低电压和栅极氧化物隧道
公开(公告)号：EP1687844A2
公开(公告)日：2006-08-09
申请号：EP04817831.3
申请日：2004-11-16
申请人： Amtel Corporation
发明人： RENNINGER, Alan, L. , SHEN, James, J.
IPC分类号： H01L21/336
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11558
摘要： A method of fabricating a non-volatile memory embedded logic circuit (Figs. 2A-2C) having a low voltage logic gate layer (92 beneath 94; 56) and tunnel oxide layer (92 beneath 86; 58) is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step (Figs. 3A (vi) and 3B (vi), thereby reducing the number of overall processing steps needed to form the devices.

97. 发明公开

EP1437774A3 Transistor storing multiple bits and method of manufacturing semiconductor memory including the same 审中-公开
标题翻译：存储多个所述晶体管的比特和制造包含其的半导体存储装置的方法的
公开(公告)号：EP1437774A3
公开(公告)日：2005-06-08
申请号：EP03029629.7
申请日：2003-12-22
申请人： Innotech Corporation
发明人： Miida, Takashi , Ichinose, Hideo
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/11526 , G11C16/0458 , G11C16/0491 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11546 , H01L29/42336 , H01L29/66825 , H01L29/7887
摘要： A flash memory includes a pair of floating gates (FG1, FG2) formed on opposite side walls (13b) of a projection (13a) and each facing one side wall (13b) and one source/drain region (BL1, BL2) via a tunnel insulation layer (15a). The floating gates (FG1, FG2) each have a substantially square cross-section in a direction perpendicular to the direction of column. The square cross-section faces one of the side walls (13b) of the projection (13a) via the tunnel insulation layer (15a) at,one of two continuous sides, faces the source/drain region (BL1, BL2) via the tunnel insulation layer (15a) at the other side, and faces a control gate (CG) via an inter-polycrystalline insulation layer (15b) at another side.

98. 发明公开

EP1347506A4 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译： HALBLEITERBAUELEMENT UND VERFAHREN ZU SEINER HERSTELLUNG
公开(公告)号：EP1347506A4
公开(公告)日：2005-04-20
申请号：EP01272543
申请日：2001-12-27
申请人： OHMI TADAHIRO
发明人： OHMI TADAHIRO , SUGAWA S , HIRAYAMA M , SHIRAI Y
IPC分类号： H01L21/28 , H01L21/306 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8239 , H01L21/8246 , H01L21/8247 , H01L27/00 , H01L27/088 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02307 , H01L21/02315 , H01L21/30604 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/12 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66757 , H01L29/78603 , H01L29/78645
摘要： A method for manufacturing a semiconductor device including a transistor and capacitors formed over a silicon substrate, wherein hydrogen present at least on a part of the surface of the silicon substrate, hydrogen is removed by exposing the surface to a plasma produced from a first inert gas, a plasma is produced from a mixture gas of a second inert gas and one or more kinds of gas molecules, and thereby to form a silicon compound layer containing at least part of the elements constituting the gas molecules is formed on the surface of the silicon substrate.
摘要翻译：一种用于制造半导体器件的方法，所述半导体器件包括形成在硅衬底上的晶体管和电容器，其中氢至少存在于所述硅衬底的一部分表面上，通过将所述表面暴露于由第一惰性气体产生的等离子体来除去氢从第二惰性气体和一种或多种气体分子的混合气体产生等离子体，从而形成包含构成气体分子的元素的至少一部分的硅化合物层形成在硅的表面上基质。

99. 发明公开

EP1391929A2 Semiconductor device and manufacturing method for the same 审中-公开
标题翻译： Halbleiterbauelement和dessen Herstellungsverfahren
公开(公告)号：EP1391929A2
公开(公告)日：2004-02-25
申请号：EP03018637.3
申请日：2003-08-20
申请人： FUJITSU LIMITED
发明人： Ariyoshi, Junichi, Fujitsu Microelectronics , Torii, Satoshi, Fujitsu Microelectronics
IPC分类号： H01L27/105 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/8234 , H01L21/283
CPC分类号： H01L27/11526 , H01L21/76897 , H01L27/105 , H01L27/11546 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： On a semiconductor substrate (30) having a gate electrode (32) and an LDD layer (33) formed thereon, an SiN film (34) to be a silicide block is formed. An opening (34a) communicating with the LDD layer (33) is provided for the SiN film (34). Impurities are introduced into the LDD layer (33) through the opening (34a) to form a source/drain layer (33a), and the surface thereof is silicided to form a silicide film (36a). Next, an interlayer insulation film (37) of SiO 2 is formed and then etched under a condition of an etching rate of SiO 2 higher than that of SiN to form a contact hole (37h) reaching the LDD layer (33) from the upper surface of the interlayer insulation film (37) via the opening (34a).
摘要翻译：在其上形成有栅极（32）和LDD层（33）的半导体衬底（30）上形成作为硅化物块的SiN膜（34）。为SiN膜（34）提供与LDD层（33）连通的开口（34a）。通过开口（34a）将杂质引入LDD层（33），形成源/漏层（33a），其表面被硅化以形成硅化物膜（36a）。接下来，形成SiO 2的层间绝缘膜（37），然后在SiO 2的蚀刻速率高于SiN的蚀刻速率的条件下进行蚀刻，形成从上部到达LDD层（33）的接触孔（37h）经由开口（34a）的层间绝缘膜（37）的表面。

100. 发明公开

EP1347506A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1347506A1
公开(公告)日：2003-09-24
申请号：EP01272543.8
申请日：2001-12-27
申请人： Ohmi, Tadahiro
发明人： OHMI, Tadahiro , SUGAWA, S.,c/o DEP. ELECTRONIC ENGINEERING GRAD. , HIRAYAMA, M., c/o DEP. ELECTRONIC ENGINEERING GRAD , SHIRAI, Y., c/o DEP. ELECTRONIC ENGINEERING GRAD.
IPC分类号： H01L21/316
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02307 , H01L21/02315 , H01L21/30604 , H01L21/3144 , H01L21/3145 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/12 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66757 , H01L29/78603 , H01L29/78645
摘要： In a fabrication method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of a silicon surface in advance, and the hydrogen is removed by exposing the silicon surface to a first inert gas plasma. Thereafter, plasma is generated by a mixed gas of a second inert gas and one or more gaseous molecules, and a silicon compound layer containing at least a part of the elements constituting the gaseous molecules is formed on the surface of the silicon gas.
摘要翻译：在包括多个硅基晶体管或电容器的半导体器件的制造方法中，预先在硅表面的至少一部分中存在氢，并且通过将硅表面暴露于第一惰性气体等离子体。此后，通过第二惰性气体和一种或多种气体分子的混合气体产生等离子体，并且在硅气体的表面上形成含有构成气态分子的至少一部分元素的硅化合物层。

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