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1. 发明授权

EP2097904B1 SPEICHERZELLE UND VERFAHREN ZUM SPEICHERN VON DATEN 有权
标题翻译：存储单元与方法用于存储数据
公开(公告)号：EP2097904B1
公开(公告)日：2011-06-15
申请号：EP07846385.8
申请日：2007-12-03
申请人： Technische Universität Berlin
发明人： BIMBERG, Dieter , GELLER, Martin , MARENT, Andreas
IPC分类号： G11C16/02 , H01L29/788
CPC分类号： H01L29/8613 , B82Y10/00 , G11C2216/08 , H01L29/127 , H01L29/205 , H01L29/8616
摘要： The invention relates, among other things, to a memory cell (10) for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals (40, 130) and a semiconductor structure (11) with a band curve (EL) that has at least one potential well (200). The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure (80). The semiconductor heterostructure and the space charge region are spatially arranged relative to one another in such a way that the semiconductor heterostructure is located within the space charge region when the maintaining voltage is applied, at the edge of or outside the space charge region when the supply voltage is applied, and within the space charge region when the discharge voltage is applied.

2. 发明公开

EP2097904A2 SPEICHERZELLE UND VERFAHREN ZUM SPEICHERN VON DATEN 有权
标题翻译：存储单元与方法用于存储数据
公开(公告)号：EP2097904A2
公开(公告)日：2009-09-09
申请号：EP07846385.8
申请日：2007-12-03
申请人： Technische Universität Berlin
发明人： BIMBERG, Dieter , GELLER, Martin , MARENT, Andreas
IPC分类号： G11C16/02 , H01L29/788
CPC分类号： H01L29/8613 , B82Y10/00 , G11C2216/08 , H01L29/127 , H01L29/205 , H01L29/8616
摘要： The invention relates, among other things, to a memory cell (10) for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals (40, 130) and a semiconductor structure (11) with a band curve (EL) that has at least one potential well (200). The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure (80). The semiconductor heterostructure and the space charge region are spatially arranged relative to one another in such a way that the semiconductor heterostructure is located within the space charge region when the maintaining voltage is applied, at the edge of or outside the space charge region when the supply voltage is applied, and within the space charge region when the discharge voltage is applied.

3. 发明公开

EP1723676A4 NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS 审中-公开
标题翻译：纳米能力和各向异性货物承运阵列内存块
公开(公告)号：EP1723676A4
公开(公告)日：2009-04-15
申请号：EP05758741
申请日：2005-03-09
申请人： NANOSYS INC
发明人： DUAN XIANGFENG , CHOW CALVIN Y H , HEALD DAVID L , NIU CHUNMING , PARCE J WALLACE , STUMBO DAVID P
IPC分类号： H01L21/28 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G11C11/56 , G11C13/02 , H01L29/423 , H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C11/56 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L29/42332 , H01L29/7881 , H01L29/7887 , Y10S977/774 , Y10S977/785 , Y10S977/936
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

4. 发明授权

EP1269477B1 MEMORY CELL WITH DOPED NANOCRYSTALS, METHOD OF FORMATION, AND OPERATION 有权
标题翻译：含掺杂纳米晶体，方法和操作内存CELL
公开(公告)号：EP1269477B1
公开(公告)日：2006-02-08
申请号：EP01920186.2
申请日：2001-03-02
申请人： Freescale Semiconductor, Inc.
发明人： MURALIDHAR, Ramachandran , MADHUKAR, Sucharita , JIANG, Bo , WHITE, Bruce, E. , SAMAVEDAM, Srikanth, B. , O'MEARA, David, L. , SADD, Michael, Alan
IPC分类号： G11C11/56 , G11C16/04 , H01L29/788
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12), a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).

5. 发明公开

EP1150302A4 SEMICONDUCTOR INTEGRATED CIRCUIT AND NONVOLATILE MEMORY ELEMENT 有权
标题翻译：集成电路和半导体非易失性存储元件
公开(公告)号：EP1150302A4
公开(公告)日：2005-09-21
申请号：EP00900823
申请日：2000-01-19
申请人： HITACHI LTD
发明人： SYUKURI SYOJI , KOMORI KAZUHIRO , OKUYAMA KOUSUKE , KUBOTA KATSUHIKO
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/28 , H01L21/8247 , H01L27/105 , G11C16/06
CPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , G11C16/0416 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/349 , G11C2216/08 , G11C2216/10 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： A nonvolatile memory element (130) constituting a flash memory is constructed such that a gate oxide film (GO2) and a gate electrode (GT2) of a transitor of another circuit formed over the same semiconductor substrate are a tunnel oxide film (GO3) and a floating gate electrode (FGT), respectively. One memory cell has a two-element one-bit construction composed of a pair of nonvolatile memory elements connected with paired complementary data lines. For the paired nonvolatile memory elements, threshold voltage states which are different from each other are set up so that they are differentially read. A word line voltage in reading operation is substantially equal to a threshold voltage (initial threshold voltage) in a thermal by equilibrium state of the non-volatile memory elements, desirably to an average of the low threshold voltage and the high threshold voltage of the memory elements. No matter whether the paired nonvolatile memory elements may be in the high threshold voltage state or in the low threshold voltage state, their threshold voltage are liable to approach the initial threshold voltage asymptotically to deteriorate in their characteristics. At this time, a word line selecting voltage is substantially equal to the initial threshold voltage, so that the read failure hardly occurs even if the characteristic deterioration of one memory element progresses relatively.

6. 发明公开

EP1328979A1 A MEMORY DEVICE AND A MEMORY ARRAY 审中-公开
标题翻译：存储器系统和存储矩阵
公开(公告)号：EP1328979A1
公开(公告)日：2003-07-23
申请号：EP00958801.3
申请日：2000-09-06
申请人： Gentech Investment Group AG.
发明人： LOSS, Daniel,Physics&Astronomy,Uni. of Basel
IPC分类号： H01L29/76
CPC分类号： H01L29/7613 , B82Y10/00 , G11C11/16 , G11C2216/08 , H01L27/222 , H01L29/127 , H01L29/221
摘要： A memory has at least one memory device (1) having an input region (3) for carrying a current, an output region (4) for carrying a current, and a three-dimensionally confined quantum region (2a) arranged to operate in the coulomb blockade regime and separating the input and output regions (3 and 4) whereby charge carriers can only pass from the input region to the output region by tunnelling through the quantum region (4). A magnetic field (Bdc) is used to control Zeeman splitting in the memory device such that the input and output regions (3 and 4) are spin polarised whereby conduction through the input and output regions is by charge carriers of one spin polarity. In one arrangement, a pulsed AC magnetic field (Bac) is used to control the spin polarisation of an uppermost charge carrier in the quantum region to control the tunnelling current through the memory device. In another arrangement the polarisation of the magnetic field applied to the output region is used to switch the memory device between a conducting and a non-conducting state so that the memory device acts as a current switch.

7. 发明授权

EP0844671B1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：使用该半导体器件和半导体存储器件
公开(公告)号：EP0844671B1
公开(公告)日：2002-11-27
申请号：EP98101633.0
申请日：1994-08-12
申请人： Hitachi, Ltd.
发明人： Yano, Kazuo , Ishii, Tomoyuki , Hashimoto, Takashi , Seki, Koichi , Aoki, Masakazu , Sakata, Takeshi , Nakagome, Yoshinobu , Takeuchi, Kan
IPC分类号： H01L29/788 , H01L29/76 , G11C16/02
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888

8. 发明公开

EP1198008A1 INFORMATION PROCESSING STRUCTURE 审中-公开
标题翻译： INFORMATIONSVERARBEITUNGSSTRUKTUR
公开(公告)号：EP1198008A1
公开(公告)日：2002-04-17
申请号：EP01915829.4
申请日：2001-03-27
申请人： Japan Science and Technology Corporation
发明人： MORIE, Takashi , IWATA, Atsushi , NAGATA, Makoto , YAMANAKA, Toshio , MATSUURA, Tomohiro
IPC分类号： H01L29/66 , H01L29/06 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L27/10
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information. Between each of the quantum dots and the power source electrode is there also formed a potential barrier that an electron is capable of directly tunneling. A capacitive coupling is provided between the information electrodes in pair and the quantum dot between them to prevent movement of an electron between the quantum dot and the information electrodes, and an electron is rendered movable by the Coulomb blockade through the quantum dot between the power source electrode and the gate electrode in response to a relative electric potential determined at the information electrodes.
摘要翻译：公开了一种信息处理结构，其由单电子电路形成，每个电子电路通过单个电子操作快速且稳定地操作。信息处理结构包括MOSFET（11）和设置在MOSFET的栅电极（12）正上方的多个量子点（13），并且每个都由纳米尺寸的微导体或微半导体制成。在每个量子点和栅电极之间形成了电子能够直接隧穿的能量势垒。在量子点和栅电极之间移动的这种电子的总数用于表示信息。在该结构中，电源电极（14）与量子点接触地设置，并且一对信息电极（15）跨越与其接触的量子点设置，以使其具有表示数据的信息。在每个量子点和电源电极之间还形成电子能够直接隧穿的势垒。在一对信息电极和它们之间的量子点之间提供电容耦合，以防止电子在量子点和信息电极之间的移动，并且电子通过库仑阻挡使得可移动通过电源之间的量子点电极和栅电极响应于在信息电极处确定的相对电位。

9. 发明公开

EP1170799A2 Elektronisches Bauelement und Verfahren zum Herstellen eines elektronischen Bauelements 审中-公开
标题翻译：电子装置和方法，用于制造电子器件
公开(公告)号：EP1170799A2
公开(公告)日：2002-01-09
申请号：EP01113210.7
申请日：2001-05-30
申请人： Infineon Technologies AG
发明人： Hofmann, Franz, Dr. , Kreupl, Franz, Dr. , Luyken, Richard Johannes, Dr. , Schloesser, Till, Dr.
IPC分类号： H01L27/115 , H01L21/8247 , H01L51/30
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5671 , G11C2213/71 , G11C2213/77 , G11C2213/81 , G11C2216/08 , H01L51/0048 , Y10S438/962 , Y10S977/943
摘要： Ein elektronisches Bauelement weist mehrere elektrisch leitende erste Nanodrähte auf, ein auf den ersten Nanodrähten aufgebrachtes Schichtensystem sowie auf dem Schichtensystem aufgebrachte zweite Nanodrähte. Die ersten und zweiten Nanodrähte sind zueinander windschief angeordnet. Das Schichtensystem ist derart eingerichtet, dass von den Nanodrähten erzeugte Ladungsträger in dem Schichtensystem gespeichert werden können.
摘要翻译：电子部件包括在导电的第一纳米线（101）; 施加到第一纳米线的层系统（103）; 和施加到所述层系统中的第二纳米线（107），该两条线被设置歪斜海誓山盟。该层系统以这样的方式搜索那样由导线中的至少一个所产生的电荷载流子可以储存在该层系统的结构。因此，一个独立claimsoft包括用于生产电子部件的过程。优选的特点：第二纳米线是一个硅纳米线或一氮化硼纳米线。第一和/或第二纳米线包含金，银，钨，铜，钽和/或钛。第一二氧化硅层（104）的层系统besteht，氮化硅层（105）和第二二氧化硅层（106）和具有用于存储电荷载流子由多晶硅制成的量子点。

10. 发明公开

EP1042818A1 DISPOSITIF DE MEMOIRE MULTINIVEAUX A BLOCAGE DE COULOMB, PROCEDE DE FABRICATION ET PROCEDE DE LECTURE/ECRITURE/EFFACEMENT D'UN TEL DISPOSITIF 有权
标题翻译：库仑阻塞多级存储器器件和相应的制造和操作过程
公开(公告)号：EP1042818A1
公开(公告)日：2000-10-11
申请号：EP98962496.0
申请日：1998-12-17
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： GAUTIER, Jacques , PALUN, Lionel
IPC分类号： H01L29/788 , H01L29/51
CPC分类号： B82Y10/00 , G11C11/5635 , G11C11/5671 , G11C2216/08 , H01L29/7882 , H01L29/7888
摘要： The invention concerns a multilevel memory device with Coulomb barrier comprising a MOSFET with floating grid. The dielectric (32) separating the floating grid (20) from the control grid (28) comprises a plurality of nanometric conducting islands (34) forming a three-dimensional structure (30) wherein they are evenly distributed.

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