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1. 发明公开

EP1837900A2 Nonvolatile semiconductor memory device 审中-公开
标题翻译： NichtflüchtigeHalbleiterspeichervorrichtung
公开(公告)号：EP1837900A2
公开(公告)日：2007-09-26
申请号：EP07005506.6
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/788 , G11C16/04 , H01L29/423 , H01L29/786
CPC分类号： H01L27/1237 , G11C16/349 , H01L21/28273 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11546 , H01L27/1203 , H01L27/1214 , H01L29/42324 , H01L29/66825 , H01L29/78696 , H01L29/7881
摘要： A semiconductor layer (14) having a channel formation region (15) provided between a pair of impurity regions (18) spaced from each other is provided, and a first insulating layer (16) a floating gate (20), a second insulating layer (22), and a control gate (24) are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.
摘要翻译：提供具有设置在彼此间隔开的一对杂质区（18）之间的沟道形成区（15）的半导体层（14），第一绝缘层（16），浮栅（20），第二绝缘层（22）和控制栅极（24）设置在半导体层的上方。形成浮栅的半导体材料优选具有比半导体层小的带隙。形成浮栅的半导体材料中的沟道形成区的带隙优选比半导体层的带隙小0.1eV以上。

2. 发明公开

EP1837917A1 Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：EP1837917A1
公开(公告)日：2007-09-26
申请号：EP07005513.2
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L29/788 , H01L29/423
CPC分类号： H01L29/42324 , H01L29/513 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.
摘要翻译：一种非易失性半导体存储装置，其特征在于，包括：在一对杂质区域之间形成有沟道形成区域的半导体基板;以及第一绝缘层，浮置栅极，第二绝缘层，以及在半导体衬底上的控制栅极。浮栅包括至少两层。优选的是，与第一绝缘层接触的浮置栅极中包括的第一层的带隙小于半导体衬底的带隙。例如，用于形成浮栅的半导体材料的带隙优选比半导体衬底中的沟道形成区域的带隙小0.1eV以上。这是因为，通过降低浮置栅电极的导带底能级比半导体衬底中的沟道形成区的导带底能级高，载流子注入性能和电荷保持性能得到改善。

3. 发明公开

EP1840947A3 Nonvolatile semiconductor memory device 审中-公开
标题翻译：的非易失性半导体存储器件
公开(公告)号：EP1840947A3
公开(公告)日：2008-08-13
申请号：EP07005504.1
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/105 , H01L27/12 , H01L29/788 , G11C11/56 , G11C16/04 , H01L29/423 , H01L29/786 , H01L27/02 , H01L27/115
CPC分类号： H01L27/1237 , G11C16/0416 , G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11546 , H01L27/1214 , H01L29/513 , H01L29/66825 , H01L29/7883 , H01L29/7885
摘要： It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer (14) including a channel forming region (15) between a pair of impurity regions (18) which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer (16), a floating gate electrode (20), a second insulating layer (22), and a control gate electrode (24) are provided. The floating gate (20) has at least a two-layer structure, and a first layer (20a) being in contact with the first insulating layer (16) preferably has a band gap smaller than that of the semiconductor layer (14). The stability of the first layer (20a) is improved by formation of a second layer (20b) of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
The first layer (20a) can comprise SiGe.

4. 发明公开

EP1760798A1 Semiconductor device and manufacturing method thereof 有权
标题翻译： Halbleiteranordnung und deren Herstellungsverfahren
公开(公告)号：EP1760798A1
公开(公告)日：2007-03-07
申请号：EP06016936.4
申请日：2006-08-14
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Suzuki, Tsuenori , Nomura, Ryoji , Yukawa, Mikio , Ohsawa, Nobuhara , Takano, Tamae , Asami, Yoshinobu , Sato, Takehisa
IPC分类号： H01L51/00
CPC分类号： H01L51/0024 , H01L27/3281 , H01L51/0021 , H01L51/003 , H01L51/56 , H01L2227/326 , H01L2251/5338 , Y02E10/549 , Y02P70/521
摘要： It is an object of the present invention to manufacture, with high yield, a semiconductor device in which an element that has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming an element-formed layer over the separation layer by forming an inorganic compound layer, a first conductive layer, and a layer containing an organic compound and forming a second conductive layer which is in contact with the layer containing an organic compound and the inorganic compound layer; and separating the separation layer and the element-formed layer from each other after pasting a first flexible substrate over the second conductive layer.
摘要翻译：本发明的目的是以高产率制造半导体器件，其中具有含有有机化合物的层的元件设置在柔性基板上。一种制造半导体器件的方法包括：在衬底上形成分离层; 通过形成无机化合物层，第一导电层和含有有机化合物的层，在分离层上形成元件形成层，形成与含有有机化合物和无机化合物的层接触的第二导电层层; 以及在所述第二导电层上粘贴第一柔性基板之后将所述分离层和所述元件形成层彼此分离。

5. 发明授权

EP1760798B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：一种半导体装置及其制造方法
公开(公告)号：EP1760798B1
公开(公告)日：2012-01-11
申请号：EP06016936.4
申请日：2006-08-14
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Suzuki, Tsuenori , Nomura, Ryoji , Yukawa, Mikio , Ohsawa, Nobuhara , Takano, Tamae , Asami, Yoshinobu , Sato, Takehisa
IPC分类号： H01L51/00
CPC分类号： H01L51/0024 , H01L27/3281 , H01L51/0021 , H01L51/003 , H01L51/56 , H01L2227/326 , H01L2251/5338 , Y02E10/549 , Y02P70/521

6. 发明公开

EP1837900A3 Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：EP1837900A3
公开(公告)日：2008-10-15
申请号：EP07005506.6
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/12 , H01L29/788 , G11C16/04 , H01L29/423 , H01L29/786
CPC分类号： H01L27/1237 , G11C16/349 , H01L21/28273 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11546 , H01L27/1203 , H01L27/1214 , H01L29/42324 , H01L29/66825 , H01L29/78696 , H01L29/7881
摘要： A semiconductor layer (14) having a channel formation region (15) provided between a pair of impurity regions (18) spaced from each other is provided, and a first insulating layer (16) a floating gate (20), a second insulating layer (22), and a control gate (24) are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.
摘要翻译：提供具有设置在彼此间隔开的一对杂质区域（18）之间的沟道形成区域（15）的半导体层（14），第一绝缘层（16），浮置栅极（20），第二绝缘层（22）和控制栅极（24）设置在半导体层上方。形成浮栅的半导体材料优选具有小于半导体层的带隙。构成浮栅的半导体材料中的沟道形成区域的带隙优选比半导体层的带隙小0.1eV以上。

7. 发明公开

EP1840947A2 Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：EP1840947A2
公开(公告)日：2007-10-03
申请号：EP07005504.1
申请日：2007-03-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yamazaki, Shunpei , Asami, Yoshinobu , Takano, Tamae , Furuno, Makoto
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/105 , H01L27/12 , H01L29/788 , G11C11/56 , G11C16/04 , H01L29/423 , H01L29/786 , H01L27/02
CPC分类号： H01L27/1237 , G11C16/0416 , G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11546 , H01L27/1214 , H01L29/513 , H01L29/66825 , H01L29/7883 , H01L29/7885
摘要： It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer (14) including a channel forming region (15) between a pair of impurity regions (18) which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer (16), a floating gate electrode (20), a second insulating layer (22), and a control gate electrode (24) are provided. The floating gate (20) has at least a two-layer structure, and a first layer (20a) being in contact with the first insulating layer (16) preferably has a band gap smaller than that of the semiconductor layer (14). The stability of the first layer (20a) is improved by formation of a second layer (20b) of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
The first layer (20a) can comprise SiGe.
摘要翻译：目的在于提供一种具有优异的写入性能和电荷保持性能的非易失性半导体存储器件。提供在彼此分开形成的一对杂质区域（18）之间包括沟道形成区域（15）的半导体层（14）。在其上层部分中，提供第一绝缘层（16），浮置栅电极（20），第二绝缘层（22）和控制栅电极（24）。浮置栅极（20）至少具有双层结构，与第一绝缘层（16）接触的第一层（20a）的带隙优选小于半导体层（14）的带隙。通过使用金属，合金或金属化合物材料形成浮置栅电极的第二层（20b），第一层（20a）的稳定性得到改善。浮栅电极的这种结构可以提高写入时的载流子的注入性和电荷保持性。第一层（20a）可以包含SiGe。

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