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91. 发明公开

EP2581938A4 HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：带集成电路的高压设备
公开(公告)号：EP2581938A4
公开(公告)日：2014-12-31
申请号：EP12757637
申请日：2012-03-13
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L21/761 , G05F3/02 , H01L27/092
CPC分类号： G05F3/02 , H01L21/761 , H01L27/0921 , H01L27/0922
摘要： A high-voltage integrated circuit device (100) comprises, in a surface layer of a p semiconductor substrate (1), an n region (3) which is a high-side floating-potential region, an n - region (4) which becomes a high-voltage junction terminating region (93), and an n - region (2) which is an L-VDD potential region. A low-side circuit portion (91) is disposed in an n - region (2). Below a pickup electrode (59) disposed in the high-voltage junction terminating region (93), a universal contact region (58) in Ohmic contact with the pickup electrode is disposed. The universal contact region (58) has a p + region (56) and an n + region (57) that are disposed in alternating contact along a surface of the p semiconductor substrate (1). By disposing the universal contact region (58) in this way, the quantity of carriers flowing into the low-side circuit portion (91) can be reduced when a negative surge voltage is input. Consequently, erroneous operation and destruction due to latchup of a logic portion of the low-side circuit portion (91) can be prevented.
摘要翻译：高电压集成电路器件（100）在p型半导体衬底（1）的表面层中包括作为高侧浮动电位区域的n区域（3），成为高压结端接区域（93）和作为L-VDD电势区域的n区域（2）。低侧电路部分（91）设置在n区（2）中。在设置在高压结终止区域（93）中的拾取电极（59）的下方设置有与拾取电极欧姆接触的通用接触区域（58）。通用接触区域（58）具有沿着p半导体衬底（1）的表面交替接触地设置的p +区域（56）和n +区域（57）。通过以这种方式设置通用接触区域（58），当输入负浪涌电压时，流入低侧电路部分（91）的载流子的数量可以减少。因此，可以防止由于低侧电路部分（91）的逻辑部分的闭锁而导致的错误操作和破坏。

92. 发明公开

EP2580782A4 SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 有权转让
标题翻译：与周长容量公路过渡肖特基二极管
公开(公告)号：EP2580782A4
公开(公告)日：2014-10-01
申请号：EP11810114
申请日：2011-06-29
申请人： IBM
发明人： ANDERSON FREDERICK G , LARY JENIFER E , RASSEL ROBERT M , STIDHAM MARK E
IPC分类号： H01L29/872 , H01L29/06 , H01L29/47
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143

93. 发明公开

EP2333827A3 Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same 失效转让
标题翻译： IV族和III族-IV的单片集成的复合半导体装置，以及其制备方法
公开(公告)号：EP2333827A3
公开(公告)日：2014-08-13
申请号：EP10015288.3
申请日：2010-12-03
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L21/8252 , H01L27/06
CPC分类号： H01L29/205 , H01L21/761 , H01L21/8252 , H01L27/0605 , H01L29/267
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

94. 发明公开

EP2706566A1 Semiconductor device and method of manufacturing same 有权转让
标题翻译：半导体器件及其制造方法
公开(公告)号：EP2706566A1
公开(公告)日：2014-03-12
申请号：EP13183690.0
申请日：2013-09-10
申请人： Renesas Electronics Corporation
发明人： Zhang, Ming , Yoshihisa, Yasuki
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/761 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66477 , H01L29/66681 , H01L29/78 , H01L29/7816 , H01L29/7835
摘要： To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p - type epitaxial region, n - type epitaxial region, n type offset region, and p type body region configuring a pn junction therewith; and further has a p + type buried region between the p - type and n - type epitaxial regions, isolation trench extending from the main surface to the p + type buried region, and trench sidewall n type region formed on at least a portion of the sidewall of the isolation trench. The n type impurity concentration in the trench sidewall n type region is higher than that in the n - type epitaxial region. The trench sidewall n type region extends along the sidewall to reach the p + type buried region.
摘要翻译：提供一种同时实现导通电阻的降低和击穿电压的增加并且抑制短路的半导体器件及其制造方法。半导体器件在其具有主表面的半导体衬底中具有构成pn结的p型外延区域，n型外延区域，n型偏移区域和p型体区域; 并且还具有在p型和n型外延区域之间的p +型掩埋区域，从主表面延伸到p +型掩埋区域的隔离沟槽，以及在侧壁的至少一部分上形成的沟槽侧壁n型区域隔离沟槽。沟槽侧壁n型区中的n型杂质浓度高于n-型外延区中的n型杂质浓度。沟槽侧壁n型区域沿着侧壁延伸以到达p +型埋入区域。

95. 发明公开

EP2243158A4 ISOLATED CMOS AND BIPOLAR TRANSISTORS, ISOLATION STRUCTURES THEREFOR AND METHODS OF FABRICATING THE SAME 有权
标题翻译：隔离的CMOS和BIOPOLARE晶体管，THEREOF隔离结构及其制造方法
公开(公告)号：EP2243158A4
公开(公告)日：2013-08-21
申请号：EP09711355
申请日：2009-02-17
申请人： ADVANCED ANALOGIC TECH INC
发明人： DISNEY DONALD R , WILLIAMS RICHARD K
IPC分类号： H01L21/8249
CPC分类号： H01L21/761 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/8222 , H01L21/82285 , H01L21/823878 , H01L21/823892 , H01L27/0825 , H01L27/0826 , H01L29/41708 , H01L29/732

96. 发明公开

EP2597680A2 Semiconductor device 审中-公开
标题翻译： Halbleiterbauelement
公开(公告)号：EP2597680A2
公开(公告)日：2013-05-29
申请号：EP12193092.9
申请日：2012-11-16
申请人： Renesas Electronics Corporation
发明人： Yanagi, Shinichiro
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7816 , H01L21/761 , H01L21/823418 , H01L27/088 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/4238 , H01L29/66659 , H01L29/7835
摘要： In the interior of a semiconductor substrate having a main surface, a first p - epitaxial region is formed, a second p - epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n + buried region is formed between the first p - epitaxial region and the second p - epitaxial region in order to electrically isolate the regions. A p + buried region having a p-type impurity concentration higher than that of the second p - epitaxial region is formed between the n + buried region and the second p - epitaxial region. The p + buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.
摘要翻译：在具有主表面的半导体衬底的内部，形成第一p-外延区，在主表面侧形成第二p-外延区，并且n型漂移区和p型体区是形成在主表面侧。在第一p-外延区域和第二p-外延区域之间形成n +掩埋区域，以便电隔离该区域。在n +掩埋区域和第二p-外延区域之间形成具有高于第二p-外延区域的p型杂质浓度的p +掩埋区域。 p +掩埋区域至少位于n型漂移区域和p型体区域之间的接合点的正下方，以避免在与n型漂移区域接触的漏极区域正下方的位置。

97. 发明公开

EP2551896A1 Substrat semi-conducteur comprenant des zones dopées formant une jonction P-N 有权转让
标题翻译： Halbleitersubstrat mit einen p-nÜbergangausbildenden dotierten Gebieten
公开(公告)号：EP2551896A1
公开(公告)日：2013-01-30
申请号：EP12177592.8
申请日：2012-07-24
申请人： Altis Semiconductor
发明人： Kellener, Olivier Philippe , Dubois, Gérard , Kanoun, Mehdi Mohamed , Mcardle, Stephen
IPC分类号： H01L21/761
CPC分类号： H01L21/761 , H01L21/8238 , H01L21/823878 , H01L21/8249
摘要： La présente invention concerne un substrat semi-conducteur (100) comprenant des zones dopées formant une jonction P-N (101), les zones dopées comprenant:
- une première zone (1) dopée selon un premier type de dopage,
- une deuxième zone (2) dopée selon un deuxième type de dopage, et
- une troisième zone (3) dopée selon le deuxième type de dopage, la troisième zone étant située entre la première zone et la deuxième zone, la concentration en élément dopant de la troisième zone étant inférieure à la concentration en élément dopant de la première zone et de la deuxième zone,

le substrat étant caractérisé en ce que la jonction P-N (101) comprend en outre une quatrième zone (4) dopée comportant :
- une première portion (4A) en contact avec la première zone, et
- une deuxième portion (4B) en contact avec la troisième zone (3), ladite deuxième portion (4B) s'étendant en direction de la deuxième zone (2), et n'étant pas en contact avec la deuxième zone (2),

ladite quatrième zone (4) étant dopée selon le même type de dopage que celui de la première zone.
摘要翻译：衬底（100）具有形成P-N结（101）的四个掺杂区（1-4），其中第一掺杂区掺杂有N型掺杂，第二和第三掺杂区掺杂有P型掺杂。第三掺杂区位于第一掺杂区和第二掺杂区之间，其中第三区的掺杂元素的浓度低于第一和第二掺杂区的掺杂元素的浓度。第四区域的掺杂元素的浓度大于第一区域的掺杂元素的最高浓度。

98. 发明公开

EP2477226A1 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR SUBSTRATE HAVING DIODE REGION AND IGBT REGION 有权转让
标题翻译：麻省理工学院麻省理工学院
公开(公告)号：EP2477226A1
公开(公告)日：2012-07-18
申请号：EP09849004.8
申请日：2009-09-07
申请人： Toyota Jidosha Kabushiki Kaisha
发明人： NAGAOKA Tatsuji , SOENO Akitaka
IPC分类号： H01L27/04 , H01L21/322 , H01L21/336 , H01L21/76 , H01L21/761 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L29/739 , H01L29/78
CPC分类号： H01L21/761 , H01L27/0727 , H01L29/32 , H01L29/7397 , H01L29/861
摘要： Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.
摘要翻译：提供了一种半导体器件，其包括其中形成二极管区域和IGBT区域的半导体衬底。在二极管区域和IGBT区域之间的范围内形成由p型半导体形成的分离区域，并且从半导体衬底的上表面延伸到比阳极区域和下端部的下端更深的位置的身体区域。二极管寿命控制区形成在二极管漂移区内。二极管寿命控制区域中的载流子寿命短于二极管寿命控制区域外的二极管漂移区域中的载流子寿命。 IGBT区域侧的二极管寿命控制区域的结束位于分离区域正下方。

99. 发明授权

EP1497858B1 HIGH FREQUENCY SIGNAL ISOLATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：隔离以防止高频率信号半导体部件
公开(公告)号：EP1497858B1
公开(公告)日：2011-09-28
申请号：EP02778496.6
申请日：2002-10-10
申请人： Freescale Semiconductor Inc.
发明人： DU, Yang, , BANERJEE, Suman, Kumar , THOMA, Rainer , DUVALLET, Alain
IPC分类号： H01L21/761 , H01L21/762
CPC分类号： H01L21/761 , H01L21/823878
摘要： A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.

100. 发明公开

EP2333827A2 Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same 失效转让
标题翻译： III-V族和IV组的单片集成的复合半导体器件及其制备方法
公开(公告)号：EP2333827A2
公开(公告)日：2011-06-15
申请号：EP10015288.3
申请日：2010-12-03
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L21/8252 , H01L27/06
CPC分类号： H01L29/205 , H01L21/761 , H01L21/8252 , H01L27/0605 , H01L29/267
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
摘要翻译：。根据一个盘游离缺失实施例，一种用于制造单片集成复合器件的方法包括：形成在一组第IV族半导体衬底一III-V族半导体本体，形成在III-V族半导体本体中的沟槽;以及形成IV族半导体本体在沟内。因此，该方法包括在所述IV族半导体本体的至少一个IV族半导体器件的制造，并且在III-V族半导体本体的至少一个III-V族半导体器件的制造。在一个中，该方法实施例还包括在所述III-V半导体主体的上表面和IV族半导体主体的上表面平坦化上呈现那些respectivement上表面基本共面。在一个中，该方法实施例还包括在所述组IV半导体本体毗邻所述沟槽的侧壁的缺陷区域制造至少一个无源器件。

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