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1. 发明授权

US4681791A Thermochromic textile material 失效
标题翻译：热变色纺织材料
公开(公告)号：US4681791A
公开(公告)日：1987-07-21
申请号：US824039
申请日：1986-01-30
申请人： Yutaka Shibahashi , Norikazu Nakasuji , Takashi Kataoka , Hiroshi Inagaki , Tutomu Kito , Masaharu Ozaki , Nobuaki Matunami , Naoya Ishimura , Katuyuki Fujita
发明人： Yutaka Shibahashi , Norikazu Nakasuji , Takashi Kataoka , Hiroshi Inagaki , Tutomu Kito , Masaharu Ozaki , Nobuaki Matunami , Naoya Ishimura , Katuyuki Fujita
IPC分类号： B41M5/28 , D05C17/00 , D06N7/04 , D06N7/06 , D06P1/00 , D06P1/44 , G01K11/16 , C09D11/06 , C09D11/12
CPC分类号： G01K11/16 , B41M5/287 , D05C17/00 , D06P1/004 , D06P1/44 , Y10S428/913 , Y10T428/23986 , Y10T428/2481 , Y10T428/24901 , Y10T428/2927 , Y10T442/3049 , Y10T442/425 , Y10T442/603
摘要： A textile material in the form of fiber, raw stock, yarn or fabric, which comprises fibers each of which is coated with a thermochromic layer containing a thermochromic pigment having a particle size satisfying the formula: ##EQU1## wherein r represents a particle size of a pigment; D represents fineness (denier) of a fiber; and d represents a density (g/cm.sup.3) of a fiber. The textile material can undergo reversible color change in a wide variety of colors and can be applied to any kind of textile products.
摘要翻译：纤维，原料，纱线或织物形式的纺织材料，其包含纤维，每个纤维均涂有含有具有满足下列通式的粒度的热变色颜料的热致变色层：其中r表示颜料; D表示纤维的细度（旦数）; d表示纤维的密度（g / cm 3）。纺织材料可以以各种颜色经历可逆的颜色变化，并且可以应用于任何种类的纺织品。

2. 发明授权

US06444313B1 Thermochromic acrylic synthetic fiber, its processed article, and process for producing thermochromic acrylic synthetic fiber 有权
标题翻译：热变色丙烯酸合成纤维，其加工制品，以及生产热变色丙烯酸合成纤维的方法
公开(公告)号：US06444313B1
公开(公告)日：2002-09-03
申请号：US09754309
申请日：2001-01-05
申请人： Yoshiaki Ono , Naoya Ishimura , Yutaka Shibahashi
发明人： Yoshiaki Ono , Naoya Ishimura , Yutaka Shibahashi
IPC分类号： D01F600
CPC分类号： D01F6/18 , D01F1/04 , D04H1/43 , D04H1/4382 , D04H3/00 , Y10S428/913 , Y10T428/2915 , Y10T428/2927 , Y10T428/2933 , Y10T428/2984
摘要： A thermochromic acrylic synthetic fiber comprising an acrylonitrile polymer in which a thermochromic pigment composition with an average particle diameter of from 0.5 &mgr;m to 30 &mgr;m is dispersedly contained in an amount of from 0.5% by weight to 40% by weight based on the weight of the polymer, and being made into fibers; the pigment composition containing (a) an electron-donating color-developing organic compound, (b) an electron-accepting compound and (c) a reaction medium that determines the temperature at which the color-developing reaction of the both compounds takes place. Also disclosed are a processed article of the above thermochromic acrylic synthetic fiber, and a process for producing the thermochromic acrylic synthetic fiber.
摘要翻译：包含丙烯腈聚合物的热致变色丙烯酸类合成纤维，其中平均粒径为0.5〜30μm的热变色颜料组合物以0.5重量％〜40重量％的量分散包含，聚合物，并制成纤维; 所述颜料组合物含有（a）给电子显色有机化合物，（b）电子接受性化合物和（c）确定发生两种化合物的显色反应的温度的反应介质。还公开了上述热变色丙烯酸类合成纤维的加工品，以及制造热变色丙烯酸类合成纤维的方法。

3. 发明授权

US08713291B2 Cache memory control device, semiconductor integrated circuit, and cache memory control method 失效
标题翻译：高速缓存存储控制装置，半导体集成电路和缓存存储器控制方法
公开(公告)号：US08713291B2
公开(公告)日：2014-04-29
申请号：US12926455
申请日：2010-11-18
申请人： Naoya Ishimura
发明人： Naoya Ishimura
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F12/0846 , G06F12/084 , G06F12/0855
摘要： A cache memory control device includes cache memories shared by arithmetic processing units, buses shared by the arithmetic processing units to transfer data, an instruction execution unit that accesses the cache memories to execute an access instruction from the arithmetic processing unit, and transfers data from the cache memory to the bus, an instruction feeding unit that feeds the access instruction to the instruction execution unit while inhibiting feeding of a subsequent access instruction for the cache memory accessed in the preceding access instruction in an execution period of the preceding access instruction and inhibiting feeding of a subsequent access instruction using the same bus as the preceding access instruction in a predetermined period, and a timing control unit that, depending on the type of the subsequent access instruction, controls the instruction executing unit to delay the transfer of the data from the cache memory to the bus.
摘要翻译：高速缓冲存储器控制装置包括由算术处理单元共享的高速缓存存储器，由算术处理单元共享的总线传送数据的指令执行单元，访问高速缓存存储器以执行来自算术处理单元的访问指令的指令执行单元，高速缓冲存储器到总线，指令馈送单元，在前一个访问指令的执行期间禁止对前一访问指令中访问的高速缓冲存储器的后续访问指令的馈送，并且禁止进给使用与预定时间段中的前一次访问指令相同的总线的后续访问指令;以及定时控制单元，其根据后续访问指令的类型来控制指令执行单元，以延迟数据从高速缓冲存储器到总线。

4. 发明申请

US20110022742A1 Processor and data transfer method 失效
标题翻译：处理器和数据传输方法
公开(公告)号：US20110022742A1
公开(公告)日：2011-01-27
申请号：US12805193
申请日：2010-07-16
申请人： Kumiko Endo , Naoya Ishimura
发明人： Kumiko Endo , Naoya Ishimura
IPC分类号： G06F13/00 , G06F5/00
CPC分类号： G06F13/1673 , G06F13/1684
摘要： A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.
摘要翻译：处理器响应于来自处理部分的请求，第一和第二存储器控制器分别经由第一和第二总线将第一和第二数据项传送到处理部分。当通过第一和第二总线同时执行数据项的传送时，其中一个数据项由缓冲器控制器传送到处理部分，另一个数据项由缓冲器控制器存储在缓冲器中。然后，在数据项中的一个数据项的传送终止之后，其他数据项由缓冲器控制器从缓冲器传送到处理部分。

5. 发明申请

US20100095068A1 CACHE MEMORY CONTROL DEVICE AND PIPELINE CONTROL METHOD 有权
标题翻译：缓存记忆控制装置和管道控制方法
公开(公告)号：US20100095068A1
公开(公告)日：2010-04-15
申请号：US12636523
申请日：2009-12-11
申请人： Koken Shimizuno , Naoya Ishimura
发明人： Koken Shimizuno , Naoya Ishimura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857
摘要： With a view to reducing the congestion of a pipeline for cache memory access in, for example, a multi-core system, a cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
摘要翻译：为了减少例如多核系统中的高速缓冲存储器访问的流水线的拥塞，高速缓存存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是在执行命令期间访问缓存内存; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

6. 发明授权

US08589636B2 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US08589636B2
公开(公告)日：2013-11-19
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

7. 发明授权

US08327079B2 Cache memory control device and pipeline control method 有权
标题翻译：缓存存储控制装置及流水线控制方式
公开(公告)号：US08327079B2
公开(公告)日：2012-12-04
申请号：US12636523
申请日：2009-12-11
申请人： Koken Shimizuno , Naoya Ishimura
发明人： Koken Shimizuno , Naoya Ishimura
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857
摘要： A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
摘要翻译：高速缓冲存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是否在执行命令期间访问高速缓冲存储器; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

8. 发明申请

US20100332758A1 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US20100332758A1
公开(公告)日：2010-12-30
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/08 , G06F12/00 , G06F9/302
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

9. 发明授权

US07849230B2 Overtake request control apparatus and overtake request control method 有权
标题翻译：超驰请求控制装置和超载请求控制方法
公开(公告)号：US07849230B2
公开(公告)日：2010-12-07
申请号：US12222228
申请日：2008-08-05
申请人： Naoya Ishimura , Hiroyuki Kojima
发明人： Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F3/00 , G06F13/00 , G06F7/38
CPC分类号： G06F13/14
摘要： A request control apparatus and a request control method are configured such that when an A type request that is an overtaking acceptable request allowed to overtake and to be overtaken among the other requests is turned to a retry matter on a pipeline, a request-order control unit performs an information renewal such that the A type request is rearranged to a place immediately preceding a B type request that is an overtaking inhibited request inhibited to overtake or to be overtaken among the other requests, and a request fetching unit fetches requests from ports by using the information renewed by the request-order control unit. Moreover, the request-order control unit is configured to perform request order control per request source.
摘要翻译：请求控制装置和请求控制方法被配置为使得当超过可接受请求的A类型请求被允许超过并且在其他请求中被超时时，将被转到管线上的重试事务，请求命令控制单元执行信息更新，使得A类型请求被重新排列到超过禁止请求的B类型请求之前禁止超过或超过其他请求的请求，并且请求提取单元从端口获取请求使用由请求单控制单元更新的信息。此外，请求顺序控制部被配置为对每个请求源执行请求顺序控制。

10. 发明授权

US08713216B2 Processor and data transfer method 失效
标题翻译：处理器和数据传输方法
公开(公告)号：US08713216B2
公开(公告)日：2014-04-29
申请号：US12805193
申请日：2010-07-16
申请人： Kumiko Endo , Naoya Ishimura
发明人： Kumiko Endo , Naoya Ishimura
IPC分类号： G06F13/00
CPC分类号： G06F13/1673 , G06F13/1684
摘要： A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.
摘要翻译：处理器响应于来自处理部分的请求，第一和第二存储器控制器分别经由第一和第二总线将第一和第二数据项传送到处理部分。当通过第一和第二总线同时执行数据项的传送时，其中一个数据项由缓冲器控制器传送到处理部分，另一个数据项由缓冲器控制器存储在缓冲器中。然后，在数据项中的一个数据项的传送终止之后，其他数据项由缓冲器控制器从缓冲器传送到处理部分。

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