专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100095068A1 CACHE MEMORY CONTROL DEVICE AND PIPELINE CONTROL METHOD 有权
标题翻译：缓存记忆控制装置和管道控制方法
公开(公告)号：US20100095068A1
公开(公告)日：2010-04-15
申请号：US12636523
申请日：2009-12-11
申请人： Koken Shimizuno , Naoya Ishimura
发明人： Koken Shimizuno , Naoya Ishimura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857
摘要： With a view to reducing the congestion of a pipeline for cache memory access in, for example, a multi-core system, a cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
摘要翻译：为了减少例如多核系统中的高速缓冲存储器访问的流水线的拥塞，高速缓存存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是在执行命令期间访问缓存内存; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

2. 发明授权

US08327079B2 Cache memory control device and pipeline control method 有权
标题翻译：缓存存储控制装置及流水线控制方式
公开(公告)号：US08327079B2
公开(公告)日：2012-12-04
申请号：US12636523
申请日：2009-12-11
申请人： Koken Shimizuno , Naoya Ishimura
发明人： Koken Shimizuno , Naoya Ishimura
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F9/3824 , G06F9/3885 , G06F12/0855 , G06F12/0857
摘要： A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.
摘要翻译：高速缓冲存储器控制装置包括：确定单元，用于确定从例如每个核心提供的命令是否在执行命令期间访问高速缓冲存储器; 以及路径切换单元，用于将被确定为访问高速缓冲存储器的命令置于流水线处理中，并且将未被确定为不访问高速缓冲存储器的命令直接输出到外部单元，而不将命令输入流水线处理。

3. 发明授权

US07689770B2 Method and system for selectively permitting cache memory access during a cache miss request 有权
标题翻译：用于在高速缓存未命中请求期间选择性地允许高速缓存存储器访问的方法和系统
公开(公告)号：US07689770B2
公开(公告)日：2010-03-30
申请号：US10986868
申请日：2004-11-15
申请人： Koken Shimizuno , Hiroyuki Kojima
发明人： Koken Shimizuno , Hiroyuki Kojima
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： A cache memory control circuit allowing an MIB to have information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is valid or not includes: a first determination section (step S41) that determines whether an index and upper address section of the request address related to the move-in request and those of the request address that is related to a preceding move-in request and has been registered in the MIB do not correspond respectively to each other, a third determination section (step S42) that determines whether an index and upper address section in the address related to the move-in request and those in the replace address that is related to the preceding move-in request and has been registered in the MIB do not correspond respectively to each other; and a tag search section (step S43) that continues the processing for the move-in request in the case where an affirmative result has been obtained both in the first and third determination sections and the replace destination is valid.
摘要翻译：一种缓存存储器控制电路，其允许MIB具有关于与移入请求相对应的替换地址的高地址部分的信息和指示替换目的地是否有效的信息包括：第一确定部（步骤S41），其确定与移入请求相关的请求地址的索引和上部地址部分以及与先前移入请求相关并且已经登记在MIB中的请求地址的索引和上部地址部分是否彼此不对应，第三确定部（步骤S42），其确定与所述移入请求相关的地址中的索引和上部地址部分以及与所述前进移动请求相关并且已经在所述MIB中登记的所述替换地址中的索引和上部地址部分是否不分别对应; 以及在第一和第三判断部分和替换目的地都被获得肯定结果的情况下继续进入移动请求的处理的标签搜索部分（步骤S43）。

4. 发明申请

US20080189719A1 OPERATION PROCESSOR APPARATUS 审中-公开
标题翻译：操作处理器装置
公开(公告)号：US20080189719A1
公开(公告)日：2008-08-07
申请号：US12062185
申请日：2008-04-03
申请人： Koken SHIMIZUNO
发明人： Koken SHIMIZUNO
IPC分类号： G06F9/54
CPC分类号： G06F9/4812 , G06F9/50
摘要： A cross call send control unit (XCSC) of an external interface unit of each CPU controls cross call transmission issued by a CPU core unit to another CPU. The XCSC has a register for keeping the processing state of the processing relating to the cross call directly associated with an issue history of the cross call for each entry.
摘要翻译：每个CPU的外部接口单元的交叉呼叫发送控制单元（XCSC）控制CPU核心单元向另一个CPU发出的交叉呼叫传输。 XCSC具有用于保持与交叉呼叫相关的处理的处理状态的寄存器，其与每个条目的交叉呼叫的发行历史直接相关联。

5. 发明申请

US20060026361A1 Cache memory control circuit and cache memory control method 有权
标题翻译：缓存存储器控制电路和缓存存储器控制方法
公开(公告)号：US20060026361A1
公开(公告)日：2006-02-02
申请号：US10986868
申请日：2004-11-15
申请人： Koken Shimizuno , Hiroyuki Kojima
发明人： Koken Shimizuno , Hiroyuki Kojima
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： A cache memory control circuit allowing an MIB to have information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is valid or not includes: a first determination section (step S41) that determines whether an index and upper address section of the request address related to the move-in request and those of the request address that is related to a preceding move-in request and has been registered in the MIB do not correspond respectively to each other, a third determination section (step S42) that determines whether an index and upper address section in the address related to the move-in request and those in the replace address that is related to the preceding move-in request and has been registered in the MIB do not correspond respectively to each other; and a tag search section (step S43) that continues the processing for the move-in request in the case where an affirmative result has been obtained both in the first and third determination sections and the replace destination is valid.
摘要翻译：一种缓存存储器控制电路，其允许MIB具有关于与移入请求相对应的替换地址的高地址部分的信息和指示替换目的地是否有效的信息包括：第一确定部（步骤S41），其中确定与移入请求相关的请求地址的索引和上部地址部分以及与先前移入请求相关并且已经被注册在MIB中的请求地址的索引和上部地址部分是否彼此不对应，第三确定部（步骤S42），其确定与所述移入请求相关的地址中的索引和上部地址部分是否与所述替换地址中的索引和上部地址部分是否与所述前进的移入请求相关并且已经被登记在 MIB不分别对应; 以及在第一和第三确定部分和替换目的地都被获得肯定结果的情况下继续进行移动请求的处理的标签搜索部分（步骤S43）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式