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1. 发明授权

US08589636B2 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US08589636B2
公开(公告)日：2013-11-19
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

2. 发明申请

US20100332758A1 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US20100332758A1
公开(公告)日：2010-12-30
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/08 , G06F12/00 , G06F9/302
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

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