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1. 发明专利

JP2011162968A Judo tatami mat 审中-公开
标题翻译： JUDO TATAMI MAT
公开(公告)号：JP2011162968A
公开(公告)日：2011-08-25
申请号：JP2010024941
申请日：2010-02-08
申请人： Nippon Hifuku Kogyo Kk , Akihiro Waku , 昭廣和久 , 日本被服工業株式会社
发明人： WAKU AKIHIRO , SHIRAISHI EIJI , FUKADA HAJIME
IPC分类号： E04F15/02
摘要： PROBLEM TO BE SOLVED: To provide Judo tatami mats which are not displaced even if an adjusting frame is not installed around a plurality of Judo tatami mats installed adjacent to each other. SOLUTION: These Judo tatami mats 3, 4, 5 are installed on the peripheral edges of a Judo hall 1 formed by the plurality of Judo tatami mats 2, 3, 4, 5. The Judo tatami mats 3, 4, 5 are connected to the Judo tatami mats 3, 4, 5 installed on the peripheral edges adjacent to the Judo tatami mats 3, 4, 5, and comprises respective connection parts surrounding the Judo tatami mats 2 installed on the inside of the Judo hall 1. Then, the Judo tatami mats 2 installed inside the Judo hall 1 are surrounded by the Judo tatami mats 3, 4, 5 installed at the peripheral edges of the Judo hall 1, restricting the movement of the Judo tatami mats 2. Thus, the Judo tatami mats are not displaced by the movement of players, dispensing with the adjusting frame to be installed around the plurality of Judo tatami mats 2 installed adjacent to each other. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使在彼此相邻安装的多个柔道榻榻榻
巾周围没有设置调整框架的情况下，也提供不偏移的柔道榻榻米。
解决方案：这些柔道榻榻榻榻榻榻米3,4,5安装在由多个柔道榻榻榻榻2,3,4,5所形成的柔道大厅1的外围边缘上。柔道榻榻榻米3,4,5 连接到安装在柔道榻榻榻榻
马3,4,5的周边边缘上的柔道榻榻榻榻榻榻米3,4,5，并包括围绕柔道大厅1内部的柔道榻榻榻
马2的各连接部分。然后，安装在柔道大厅1内的柔道榻榻榻米2被安装在柔道大厅1的周边边缘的柔道榻榻榻米3,4,5围拢，限制柔道榻榻米2的移动。于是，柔道榻榻米不会被玩家的移动所取代，而是分配安装在彼此相邻安置的多个Judo榻榻米2周围的调整框架。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2013023817A Judo tatami mat 审中-公开
标题翻译： JUDO TATAMI MAT
公开(公告)号：JP2013023817A
公开(公告)日：2013-02-04
申请号：JP2011156187
申请日：2011-07-15
申请人： Nippon Hifuku Kogyo Kk , 日本被服工業株式会社 , Akihiro Waku , 昭廣和久
发明人： WAKU AKIHIRO , SHIRAISHI EIJI , FUKADA HAJIME , SUGIMOTO KAZUNORI
IPC分类号： E04F15/02 , A44B18/00
摘要： PROBLEM TO BE SOLVED: To provide a judo tatami mat, which does not get out of alignment even when no alignment frame is placed around a plurality of the judo tatami mats laid adjacent to each other.SOLUTION: Judo tatami mats 3, 4, and 5 are placed along the peripheral edge of a judo hall 1 composed of a plurality of judo tatami mats 2, 3, 4, and 5, and are joined with other judo tatami mats 3, 4, and 5 placed adjacent to the aforesaid judo tatami mats 3, 4, and 5 along the aforesaid peripheral edge, forming a link part surrounding judo tatami mats 2 placed in the inner part of the judo hall 1. With this arrangement, the judo tatami mats 2 placed in the inner part of the judo hall 1 are surrounded by the judo tatami mats 3, 4, and 5 placed along the peripheral edge of the judo hall 1, being inhibited from movement, so that they are not moved out of alignment by movement of athletes, making it unnecessary to place an alignment frame around the plurality of judo tatami mats 2 placed adjacent to each other.
摘要翻译：要解决的问题：提供柔软的榻榻米，即使在彼此相邻放置的多个柔道榻榻榻
巾周围没有对准框架也不会失去对准的柔软榻榻米。
解决方案：柔道榻榻榻米3,4和5沿着由多个柔道榻榻榻榻2,3,4和5组成的柔道大厅1的外围边缘放置，并与其他柔道榻榻榻米 3，4和5沿着上述周边边缘邻近上述柔道榻榻榻榻榻
马3，4和5，形成一个围绕柔道榻榻榻榻2的连接部分，放置在柔道大厅1的内部。放置在柔道厅1内部的柔道榻榻榻2被沿着柔道大厅1的周边边缘放置的柔道榻榻榻榻3,4和5包围，被禁止运动，使得它们不被移动通过运动员的运动不对齐，使得不需要在彼此相邻放置的多个柔道榻榻榻2周围放置对准框架。版权所有（C）2013，JPO＆INPIT

3. 发明授权

US08589636B2 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US08589636B2
公开(公告)日：2013-11-19
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

4. 发明申请

US20100332758A1 Cache memory device, processor, and processing method 失效
标题翻译：缓存存储器，处理器和处理方法
公开(公告)号：US20100332758A1
公开(公告)日：2010-12-30
申请号：US12801869
申请日：2010-06-29
申请人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
发明人： Akihiro Waku , Naoya Ishimura , Hiroyuki Kojima
IPC分类号： G06F12/08 , G06F12/00 , G06F9/302
CPC分类号： G06F12/0888
摘要： A cache memory device includes: a data memory storing data written by an arithmetic processing unit; a connecting unit connecting an input path from the arithmetic processing unit to the data memory and an output path from the data memory to a main storage unit; a selecting unit provided on the output path to select data from the data memory or data from the arithmetic processing unit via the connecting unit, and to transfer the selected data to the output path; and a control unit controlling the selecting unit such that the data from the data memory is transferred to the output path when the data is written from the data memory to the main storage unit, and such that the data is transferred to the output path via the connecting unit when the data is written from the arithmetic processing unit to the main storage unit.
摘要翻译：高速缓冲存储器装置包括：数据存储器，存储由算术处理单元写入的数据; 连接单元，连接从算术处理单元到数据存储器的输入路径以及从数据存储器到主存储单元的输出路径; 选择单元，设置在所述输出路径上以经由所述连接单元从所述数据存储器选择数据或来自所述算术处理单元的数据，并将所选择的数据传送到所述输出路径; 以及控制单元，其控制所述选择单元，使得当所述数据从所述数据存储器写入所述主存储单元时，来自所述数据存储器的数据被传送到所述输出路径，并且使得所述数据经由所述数据存储器被传送到所述输出路径当从算术处理单元向主存储单元写入数据时，连接单元。

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