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1. 发明申请

US20090321819A1 Semiconductor device having super junction 有权
标题翻译：具有超结的半导体器件
公开(公告)号：US20090321819A1
公开(公告)日：2009-12-31
申请号：US12314786
申请日：2008-12-16
申请人： Yuma Kagata , Jun Sakakibara , Hitoshi Yamaguchi
发明人： Yuma Kagata , Jun Sakakibara , Hitoshi Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.
摘要翻译：一种半导体器件包括：第一半导体层; PN列层，其具有第一和第二列层; 和第二半导体层。第一和第二列层中的每一个包括与水平方向一起交替布置的第一和第二列。通过从第一列中的杂质量减去第二列中的杂质量，第一和第二列层分别具有在预定深度处限定的第一和第二杂质量差异。第一杂质量差为常数和正数。第二杂质量差为常数和负数。

2. 发明授权

US07859048B2 Semiconductor device having super junction 有权
标题翻译：具有超结的半导体器件
公开(公告)号：US07859048B2
公开(公告)日：2010-12-28
申请号：US12314786
申请日：2008-12-16
申请人： Yuma Kagata , Jun Sakakibara , Hitoshi Yamaguchi
发明人： Yuma Kagata , Jun Sakakibara , Hitoshi Yamaguchi
IPC分类号： H01L29/68
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.
摘要翻译：一种半导体器件包括：第一半导体层; PN列层，其具有第一和第二列层; 和第二半导体层。第一和第二列层中的每一个包括与水平方向交替布置的第一和第二列。第一和第二列分别具有通过从第一列中的杂质量减去第二列中的杂质量而在预定深度定义的第一和第二杂质量差异。第一杂质量差为常数和正数。第二杂质量差为常数和负数。

3. 发明授权

US08384153B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08384153B2
公开(公告)日：2013-02-26
申请号：US13177707
申请日：2011-07-07
申请人： Tsuyoshi Yamamoto , Masakiyo Sumitomo , Hitoshi Yamaguchi , Nozomu Akagi , Yuma Kagata
发明人： Tsuyoshi Yamamoto , Masakiyo Sumitomo , Hitoshi Yamaguchi , Nozomu Akagi , Yuma Kagata
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.
摘要翻译：半导体器件包括：衬底; 用于提供超结结构的衬底上的多个第一和第二导电类型区域; 超级结结构上的沟道层; 沟道层中的第一导电类型层; 沟道层中的接触第二导电类型区域; 通过栅极绝缘膜在沟道层上形成栅电极; 沟道层上的表面电极; 衬底上的与超结结构相反的背面电极; 和嵌入式第二导电类型区域。嵌入的第二导电类型区域设置在相应的第二导电类型区域中，突出到沟道层中，并且与接触第二导电类型区域接触。嵌入的第二导电类型区域的杂质浓度高于沟道层，并且在相应的第二导电类型区域的位置具有最大的杂质浓度。

4. 发明授权

US07928470B2 Semiconductor device having super junction MOS transistor and method for manufacturing the same 有权
标题翻译：具有超结MOS晶体管的半导体器件及其制造方法
公开(公告)号：US07928470B2
公开(公告)日：2011-04-19
申请号：US11598646
申请日：2006-11-14
申请人： Hitoshi Yamaguchi , Jun Sakakibara
发明人： Hitoshi Yamaguchi , Jun Sakakibara
IPC分类号： H01L29/66
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.
摘要翻译：具有超结MOS晶体管的半导体器件包括：半导体衬底; 在所述基板上的第一半导体层; 在所述第一半导体层上的第二半导体层; 在第二半导体层的第一表面部分上的沟道形成区; 在所述沟道形成区域的第一表面部分上的源极区域; 在所述沟道形成区域的第二表面部分上的源极接触区域; 在沟道形成区域的第三表面部分上的栅电极; 源极区域和源极接触区域上的源极电极; 位于衬底背面的漏电极; 以及在所述第二半导体层的第二表面部分上的阳极电极。阳极电极提供肖特基势垒二极管。

5. 发明授权

US07564095B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07564095B2
公开(公告)日：2009-07-21
申请号：US11439971
申请日：2006-05-25
申请人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
发明人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/66704 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7823 , H01L29/7825
摘要： A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.
摘要翻译：半导体器件包括：半导体衬底; 具有包括杂质层和沟槽的半导体元件的元件区，其中所述杂质层设置在所述沟槽中，并且其中所述沟槽设置在所述衬底的主表面上; 以及设置在所述元件区域周围的场区域。沟槽是多个条纹沟槽的聚集，使得元件区域具有多边形形状。场区域包括在元件区域的周边上与多边形形状的一侧一起设置的虚拟沟槽。虚拟沟槽具有与沟槽相同的宽度和纵向方向。场区域还包括设置在虚拟沟槽中的杂质层。

6. 发明申请

US20060286751A1 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US20060286751A1
公开(公告)日：2006-12-21
申请号：US11439971
申请日：2006-05-25
申请人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
发明人： Yasushi Urakami , Jun Sakakibara , Hitoshi Yamaguchi
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/66704 , H01L29/66734 , H01L29/7809 , H01L29/7811 , H01L29/7823 , H01L29/7825
摘要： A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.

7. 发明授权

US07838995B2 Semiconductor device having p-n column portion 有权
标题翻译：具有p-n列部分的半导体器件
公开(公告)号：US07838995B2
公开(公告)日：2010-11-23
申请号：US12216808
申请日：2008-07-10
申请人： Yasushi Urakami , Hitoshi Yamaguchi , Jun Sakakibara
发明人： Yasushi Urakami , Hitoshi Yamaguchi , Jun Sakakibara
IPC分类号： H01L23/48
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.
摘要翻译：一种半导体器件包括：第一半导体层; 在第一半导体层上的p-n列部分，并且包括交替布置的第二和第三半导体层; 以及与p-n列部分相邻并包括第四半导体层的周边部分。端部第二半导体层的杂质量等于或大于其它第二半导体层的一半。第三半导体层包括与端部第二半导体层相邻的大杂质量部分。大杂质量部分包括杂质量大于其它第三半导体层的杂质量的至少一个第三半导体层。

8. 发明申请

US20050045996A1 Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench 审中-公开
标题翻译：具有外延填充沟槽的半导体器件和具有外延填充沟槽的半导体器件的制造方法
公开(公告)号：US20050045996A1
公开(公告)日：2005-03-03
申请号：US10950423
申请日：2004-09-28
申请人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
发明人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
IPC分类号： H01L21/20 , H01L21/336 , H01L29/04 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/78 , H01L21/332 , H01L31/036
CPC分类号： H01L29/781 , H01L29/045 , H01L29/0634 , H01L29/4232 , H01L29/4238 , H01L29/66674 , H01L29/7801 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
摘要翻译：半导体器件包括半导体衬底和半导体层。半导体衬底具有作为Si {100}表面的主表面。基板在主表面具有沟槽。半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。底表面和长侧壁表面是Si {100}表面。

9. 发明授权

US06696323B2 Method of manufacturing semiconductor device having trench filled up with gate electrode 有权
标题翻译：制造具有填充有栅电极的沟槽的半导体器件的方法
公开(公告)号：US06696323B2
公开(公告)日：2004-02-24
申请号：US10340746
申请日：2003-01-13
申请人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
发明人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L21332
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译：在半导体器件中，p型基极区域设置在n型衬底中，从衬底的主表面沿垂直于主表面的方向延伸。 n +型源极区域在垂直方向上从主表面在p型基极区域中延伸，并且n +型漏极区域在p型基极区域中与p型基极区域分开延伸，漂移区域。形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。栅电极通过栅极绝缘膜形成在沟槽中。因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

10. 发明授权

US08890252B2 Semiconductor device having switching element and free wheel diode and method for controlling the same 有权
标题翻译：具有开关元件和续流二极管的半导体器件及其控制方法
公开(公告)号：US08890252B2
公开(公告)日：2014-11-18
申请号：US13190798
申请日：2011-07-26
申请人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
发明人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
IPC分类号： H01L21/70 , H01L21/78 , H01L29/739 , H01L29/78 , H01L29/10 , H01L29/40 , H01L29/49 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/861 , H02M7/00
CPC分类号： H01L29/7813 , H01L27/0629 , H01L27/0635 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4983 , H01L29/66734 , H01L29/7391 , H01L29/7393 , H01L29/7397 , H01L29/7398 , H01L29/7805 , H01L29/7819 , H01L29/7825 , H01L29/7831 , H01L29/861 , H01L2924/0002 , H02M7/003 , H01L2924/00
摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
摘要翻译：一种半导体器件包括：具有漂移层的开关元件; 基地区在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

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