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1. 发明授权

US06696323B2 Method of manufacturing semiconductor device having trench filled up with gate electrode 有权
标题翻译：制造具有填充有栅电极的沟槽的半导体器件的方法
公开(公告)号：US06696323B2
公开(公告)日：2004-02-24
申请号：US10340746
申请日：2003-01-13
申请人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
发明人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L21332
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译：在半导体器件中，p型基极区域设置在n型衬底中，从衬底的主表面沿垂直于主表面的方向延伸。 n +型源极区域在垂直方向上从主表面在p型基极区域中延伸，并且n +型漏极区域在p型基极区域中与p型基极区域分开延伸，漂移区域。形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。栅电极通过栅极绝缘膜形成在沟槽中。因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

2. 发明授权

US06525375B1 Semiconductor device having trench filled up with gate electrode 有权
标题翻译：具有填充有栅电极的沟槽的半导体器件
公开(公告)号：US06525375B1
公开(公告)日：2003-02-25
申请号：US09688154
申请日：2000-10-16
申请人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
发明人： Hitoshi Yamaguchi , Toshio Sakakibara , Jun Sakakibara , Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译：在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。栅电极通过栅极绝缘膜形成在沟槽中。因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

3. 发明授权

US06495883B2 Trench gate type semiconductor device and method of manufacturing 有权
标题翻译：沟槽型半导体器件及其制造方法
公开(公告)号：US06495883B2
公开(公告)日：2002-12-17
申请号：US10060379
申请日：2002-02-01
申请人： Takumi Shibata , Shoichi Yamauchi , Yasushi Urakami , Toshiyuki Morishita
发明人： Takumi Shibata , Shoichi Yamauchi , Yasushi Urakami , Toshiyuki Morishita
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+0 type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.
摘要翻译：半导体器件在沟槽底部具有比用于沟道的侧壁高的栅极氧化膜的介电强度。制备具有（110）基板平面取向的n + 0型基板1，并且形成通道的沟槽的侧壁在（100）平面中。沟槽的另一个非通道形成侧壁在（110）平面中。因此，非通道形成侧壁和沟槽底部中的栅极氧化膜7的生长速度比形成沟道的侧壁的生长速度快。结果，在非沟道形成侧壁和沟槽底部处的膜厚度大于沟道形成侧壁的膜厚度。因此，器件具有高迁移率，并且由于栅极氧化膜7的厚度的部分减小而不会降低介电强度。这实现了导通电阻的降低和半导体器件的介电强度的增加。

4. 发明授权

US06630389B2 Method for manufacturing semiconductor device 有权
公开(公告)号：US06630389B2
公开(公告)日：2003-10-07
申请号：US10059030
申请日：2002-01-30
申请人： Takumi Shibata , Toshiyuki Morishita
发明人： Takumi Shibata , Toshiyuki Morishita
IPC分类号： H01L2176
CPC分类号： H01L21/3247 , H01L21/28167 , H01L21/324 , H01L29/4236 , H01L29/66348 , H01L29/7813
摘要： In a trench-gate type power MOSFET in which a gate electrode is formed on a gate oxide layer formed on a surface of a wall defining a trench, the trench is annealed by heating, for example, at the temperature between 1050° C. and 1150° C. in a hydrogen atmosphere before the gate oxide layer is formed. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontal width, so that a trench having a high aspect ratio is provided while leak current at a PN junction is prevented. In addition, the breakdown voltage of the gate oxide layer is prevented from being lowered.

5. 发明授权

US07855384B2 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US07855384B2
公开(公告)日：2010-12-21
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L29/04 , H01L29/94
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

6. 发明申请

US20070241338A1 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US20070241338A1
公开(公告)日：2007-10-18
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

7. 发明授权

US5777365A Semiconductor device having a silicon-on-insulator structure 失效
标题翻译：具有绝缘体上硅结构的半导体器件
公开(公告)号：US5777365A
公开(公告)日：1998-07-07
申请号：US721626
申请日：1996-09-26
申请人： Hitoshi Yamaguchi , Toshiyuki Morishita , Hiroaki Himi
发明人： Hitoshi Yamaguchi , Toshiyuki Morishita , Hiroaki Himi
IPC分类号： H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/10 , H01L29/78 , H01L29/786 , H01L27/02
CPC分类号： H01L29/7824 , H01L21/76264 , H01L29/66681 , H01L21/76275 , H01L21/76286 , H01L29/78603
摘要： A semiconductor device of SOI structure exhibits a excellent heat-radiating characteristic while assuring breakdown-voltage and element-isolating performance. A buried silicon oxide film having a thickness required by the breakdown-voltage of a semiconductor element is buried between a SOI layer and a silicon substrate. A SOI layer is divided into island silicon regions by a groove for electrical-isolation use, and the groove is filled with dielectric such as an oxide film and polycrystalline silicon. In an island silicon region, a LDMOS transistor having high breakdown voltage may be formed as the semiconductor element, and potential distribution is created in accordance with a voltage application to the semiconductor element. The buried silicon oxide film at a region where low electric potential is distributed, for example a region below a grounded well region of the LDMOS transistor, is made thin. Through the thin portion of the buried silicon oxide film, heat generated by the operation of the semiconductor element can easily be propagated to the silicon substrate and radiated.
摘要翻译： SOI结构的半导体器件在确保击穿电压和元件隔离性能的同时表现出优异的散热特性。具有半导体元件的击穿电压所需的厚度的掩埋氧化硅膜被掩埋在SOI层和硅衬底之间。 SOI层通过用于电绝缘的沟槽被划分为岛状硅区域，并且沟槽填充有诸如氧化物膜和多晶硅的电介质。在岛状硅区域中，可以形成具有高击穿电压的LDMOS晶体管作为半导体元件，并且根据对半导体元件的施加电压产生电位分布。在低电位分布的区域（例如LDMOS晶体管的接地阱区域下方的区域）中的掩埋氧化硅膜变薄。通过掩埋氧化硅膜的薄壁部分，可以容易地将由半导体元件的工作产生的热量传播到硅衬底并辐射。

8. 发明授权

US6118152A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6118152A
公开(公告)日：2000-09-12
申请号：US181613
申请日：1998-10-28
申请人： Hitoshi Yamaguchi , Toshiyuki Morishita , Toshimasa Yamamoto
发明人： Hitoshi Yamaguchi , Toshiyuki Morishita , Toshimasa Yamamoto
IPC分类号： H01L21/02 , H01L21/331 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/72
CPC分类号： H01L29/402 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/66325 , H01L29/66681 , H01L29/7394 , H01L29/7813 , H01L29/7824 , H01L29/7835 , H01L29/78624 , H01L21/76275 , H01L21/76286
摘要： A silicon layer provided in a silicon substrate through a buried oxide film includes a silicon island partitioned by a trench. A surface of the silicon island in the trench is covered with a side wall oxide film, and LDMOS transistors are formed in the trench. A first impurity-doped polysilicon layer for applying a substrate potential is disposed between the buried oxide film and the substrate, and a second impurity-doped polysilicon layer is buried in the trench to communicate with the first impurity-doped polysilicon layer. Further, electrodes for applying the substrate potential are disposed on the second impurity-doped polysilicon layer. Accordingly, the substrate potential can be readily applied from the surface of the silicon layer.
摘要翻译：通过掩埋氧化膜设置在硅衬底中的硅层包括由沟槽分隔的硅岛。沟槽中的硅岛的表面被侧壁氧化膜覆盖，并且在沟槽中形成LDMOS晶体管。用于施加衬底电位的第一杂质掺杂多晶硅层设置在掩埋氧化膜和衬底之间，并且第二掺杂杂质的多晶硅层埋入沟槽中以与第一杂质掺杂多晶硅层连通。此外，用于施加衬底电位的电极设置在第二杂质掺杂多晶硅层上。因此，可以容易地从硅层的表面施加衬底电位。

9. 发明申请

US20110308355A1 Adsorption agent for noble metal, method for manufacturing the same, and method for recovering noble metal 有权
标题翻译：贵金属用吸附剂及其制造方法以及回收贵金属的方法
公开(公告)号：US20110308355A1
公开(公告)日：2011-12-22
申请号：US13134870
申请日：2011-06-20
申请人： Hisaya Kato , Toshiyuki Morishita , Kinya Atsumi , Minoru Kurata , Katsutoshi Inoue , Hidetaka Kawakita , Keisuke Ohto
发明人： Hisaya Kato , Toshiyuki Morishita , Kinya Atsumi , Minoru Kurata , Katsutoshi Inoue , Hidetaka Kawakita , Keisuke Ohto
IPC分类号： C22B11/00 , C12N1/00 , C22B9/02 , C12N1/12
CPC分类号： C02F1/286 , B01J20/305 , B01J20/3078 , B01J20/3085 , B01J20/3204 , B01J20/3248 , B01J2220/4843 , B01J2220/4875 , C02F3/322 , C02F2101/20
摘要： A noble metal adsorption agent includes algae or residue of algae having an amino group as a functional group. A noble metal is retrieved by a method including: adsorbing the noble metal on the noble metal adsorption agent; and retrieving the noble metal. The noble metal is solved in a liquid. Thus, by using the noble metal adsorption agent, the noble metal is selectively retrieved.
摘要翻译：贵金属吸附剂包括具有氨基作为官能团的藻类或藻类残留物。通过以下方法回收贵金属：将贵金属吸附在贵金属吸附剂上; 并检索贵金属。贵金属溶解在液体中。因此，通过使用贵金属吸附剂，选择性地回收贵金属。

10. 发明授权

US07905090B2 Steam engine 有权
标题翻译：蒸汽机
公开(公告)号：US07905090B2
公开(公告)日：2011-03-15
申请号：US12228414
申请日：2008-08-11
申请人： Shinichi Yatsuzuka , Shuzo Oda , Yasumasa Hagiwara , Toshiyuki Morishita , Katsuya Komaki
发明人： Shinichi Yatsuzuka , Shuzo Oda , Yasumasa Hagiwara , Toshiyuki Morishita , Katsuya Komaki
IPC分类号： F01B29/10
CPC分类号： F01K27/005
摘要： A steam engine has a pipe shaped fluid container, a heating and cooling devices respectively provided at a heating and cooling portions of the fluid container, and an output device connected to the fluid container, so that the output device is operated by the fluid pressure change in the fluid container, to generate an electric power. In such a steam engine, an inner radius “r1” of the cooling portion is made to almost equal to a depth “δ1” of the thermal penetration, which is calculated by the following formula (1); δ 1 = 2 ⁢ a 1 ω ( 1 ) wherein, “a1” is a heat diffusivity of the working fluid at its low pressure, and “ω” is an angular frequency of the movement of the working fluid.
摘要翻译：蒸汽发动机具有管状流体容器，分别设置在流体容器的加热和冷却部分处的加热和冷却装置以及连接到流体容器的输出装置，使得输出装置由流体压力变化在流体容器中产生电力。在这样的蒸汽机中，冷却部的内半径“r1”与通过下式（1）计算出的热贯穿深度“δ1”大致相等。 δ1 = 2a 1ω（1）其中，“a1”是工作流体在其低压下的热扩散率，“ω”是工作流体的运动的角频率。

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