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1. 发明授权

US08384153B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08384153B2
公开(公告)日：2013-02-26
申请号：US13177707
申请日：2011-07-07
申请人： Tsuyoshi Yamamoto , Masakiyo Sumitomo , Hitoshi Yamaguchi , Nozomu Akagi , Yuma Kagata
发明人： Tsuyoshi Yamamoto , Masakiyo Sumitomo , Hitoshi Yamaguchi , Nozomu Akagi , Yuma Kagata
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.
摘要翻译：半导体器件包括：衬底; 用于提供超结结构的衬底上的多个第一和第二导电类型区域; 超级结结构上的沟道层; 沟道层中的第一导电类型层; 沟道层中的接触第二导电类型区域; 通过栅极绝缘膜在沟道层上形成栅电极; 沟道层上的表面电极; 衬底上的与超结结构相反的背面电极; 和嵌入式第二导电类型区域。嵌入的第二导电类型区域设置在相应的第二导电类型区域中，突出到沟道层中，并且与接触第二导电类型区域接触。嵌入的第二导电类型区域的杂质浓度高于沟道层，并且在相应的第二导电类型区域的位置具有最大的杂质浓度。

2. 发明申请

US20120025874A1 SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENT AND FREE WHEEL DIODE AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：具有切换元件和自由轮二极管的半导体器件及其控制方法
公开(公告)号：US20120025874A1
公开(公告)日：2012-02-02
申请号：US13190798
申请日：2011-07-26
申请人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
发明人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
IPC分类号： H03K17/06 , H01L29/739
CPC分类号： H01L29/7813 , H01L27/0629 , H01L27/0635 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4983 , H01L29/66734 , H01L29/7391 , H01L29/7393 , H01L29/7397 , H01L29/7398 , H01L29/7805 , H01L29/7819 , H01L29/7825 , H01L29/7831 , H01L29/861 , H01L2924/0002 , H02M7/003 , H01L2924/00
摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
摘要翻译：一种半导体器件包括：具有漂移层的开关元件; 基地区在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

3. 发明授权

US08890252B2 Semiconductor device having switching element and free wheel diode and method for controlling the same 有权
标题翻译：具有开关元件和续流二极管的半导体器件及其控制方法
公开(公告)号：US08890252B2
公开(公告)日：2014-11-18
申请号：US13190798
申请日：2011-07-26
申请人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
发明人： Hirotaka Saikaku , Tsuyoshi Yamamoto , Shoji Mizuno , Masakiyo Sumitomo , Tetsuo Fujii , Jun Sakakibara , Hitoshi Yamaguchi , Yoshiyuki Hattori , Rie Taguchi , Makoto Kuwahara
IPC分类号： H01L21/70 , H01L21/78 , H01L29/739 , H01L29/78 , H01L29/10 , H01L29/40 , H01L29/49 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/861 , H02M7/00
CPC分类号： H01L29/7813 , H01L27/0629 , H01L27/0635 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4983 , H01L29/66734 , H01L29/7391 , H01L29/7393 , H01L29/7397 , H01L29/7398 , H01L29/7805 , H01L29/7819 , H01L29/7825 , H01L29/7831 , H01L29/861 , H01L2924/0002 , H02M7/003 , H01L2924/00
摘要： A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
摘要翻译：一种半导体器件包括：具有漂移层的开关元件; 基地区在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

4. 发明授权

US08278731B2 Semiconductor device having SOI substrate and method for manufacturing the same 有权
标题翻译：具有SOI衬底的半导体器件及其制造方法
公开(公告)号：US08278731B2
公开(公告)日：2012-10-02
申请号：US12289773
申请日：2008-11-04
申请人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
发明人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
IPC分类号： H01L21/762 , H01L27/12
CPC分类号： H01L21/823481 , H01L21/26533 , H01L21/76243 , H01L21/76264 , H01L21/823487 , H01L21/84 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L29/0634 , H01L29/0653 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
摘要翻译：半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。沟槽分离元件分离第一区域和第二区域。第一电路设置在第一区域的SOI层中。第二电路设置在第二区域的支撑层中。

5. 发明申请

US20090127624A1 Semiconductor device having soi substrate and method for manufacturing the same 有权
标题翻译：具有硅衬底的半导体器件及其制造方法
公开(公告)号：US20090127624A1
公开(公告)日：2009-05-21
申请号：US12289773
申请日：2008-11-04
申请人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
发明人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
IPC分类号： H01L21/762 , H01L27/12
CPC分类号： H01L21/823481 , H01L21/26533 , H01L21/76243 , H01L21/76264 , H01L21/823487 , H01L21/84 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L29/0634 , H01L29/0653 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
摘要翻译：半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。沟槽分离元件分离第一区域和第二区域。第一电路设置在第一区域的SOI层中。第二电路设置在第二区域的支撑层中。

6. 发明授权

US08815701B2 Method for manufacturing semiconductor device having SOI substrate 有权
标题翻译：具有SOI衬底的半导体器件的制造方法
公开(公告)号：US08815701B2
公开(公告)日：2014-08-26
申请号：US13546040
申请日：2012-07-11
申请人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
发明人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
IPC分类号： H01L21/762 , H01L27/12 , H01L27/06 , H01L21/8234 , H01L27/02 , H01L21/84 , H01L29/06 , H01L29/78 , H01L21/265
CPC分类号： H01L21/823481 , H01L21/26533 , H01L21/76243 , H01L21/76264 , H01L21/823487 , H01L21/84 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L29/0634 , H01L29/0653 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
摘要翻译：半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。沟槽分离元件分离第一区域和第二区域。第一电路设置在第一区域的SOI层中。第二电路设置在第二区域的支撑层中。

7. 发明申请

US20120302036A1 SEMICONDUCTOR DEVICE HAVING SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有SOI衬底的半导体器件及其制造方法
公开(公告)号：US20120302036A1
公开(公告)日：2012-11-29
申请号：US13546040
申请日：2012-07-11
申请人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
发明人： Masakiyo Sumitomo , Makoto Asai , Nozomu Akagi , Yasuhiro Kitamura , Hiroki Nakamura , Tetsuo Fujii
IPC分类号： H01L21/762
CPC分类号： H01L21/823481 , H01L21/26533 , H01L21/76243 , H01L21/76264 , H01L21/823487 , H01L21/84 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L29/0634 , H01L29/0653 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
摘要翻译：半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。沟槽分离元件分离第一区域和第二区域。第一电路设置在第一区域的SOI层中。第二电路设置在第二区域的支撑层中。

8. 发明授权

US09178050B2 Load-short-circuit-tolerant semiconductor device having trench gates 有权
标题翻译：具有沟槽栅极的负载短路容忍半导体器件
公开(公告)号：US09178050B2
公开(公告)日：2015-11-03
申请号：US14347077
申请日：2012-09-13
申请人： Yasushi Higuchi , Shigemitsu Fukatsu , Masakiyo Sumitomo
发明人： Yasushi Higuchi , Shigemitsu Fukatsu , Masakiyo Sumitomo
IPC分类号： H01L29/66 , H01L29/739 , H01L29/08 , H01L29/423 , H01L29/10
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/0843 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66348
摘要： In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L1 (>0) of the ineffective region in the y-direction, a length D1 of the communication portion in the z-direction, and a length D2 of the bottom portion in the z-direction satisfy L1≦2(D1+D2). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.
摘要翻译：在半导体器件中，沟槽栅极具有漂移层中的底部部分和从基底层的表面延伸以与底部部分连通的连通部分。相邻底部之间的距离小于x方向上的相邻连通部之间的距离。相邻沟槽栅极之间的区域在y方向上分成有效区域作为电子注入源和不用作电子注入源的无效区域。 y方向无效区域的间隔L1（> 0），z方向上的连通部的长度D1和z方向的底部的长度D2满足L1＆nlE; 2（D1 + D2）。 z方向与由x方向和y方向相互正交的x-y平面正交。

9. 发明申请

US20120025794A1 DRIVE CONTROLLER 有权
标题翻译：驱动控制器
公开(公告)号：US20120025794A1
公开(公告)日：2012-02-02
申请号：US13191765
申请日：2011-07-27
申请人： Takeshi INOUE , Masakiyo Sumitomo
发明人： Takeshi INOUE , Masakiyo Sumitomo
IPC分类号： G05F1/00
CPC分类号： H02M3/158 , H01L2224/05554 , H01L2224/0603 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19107 , H02M2003/1555 , H01L2924/00 , H01L2924/00012
摘要： A drive controller for driving an inductive load connected to a node between first and second switches connected in series with a direct current voltage source includes a first diode, a series circuit of a second diode and an inductor, and a control circuit. The first diode is a parasitic diode of the first switch and connected in antiparallel with the first switch. The series circuit is connected in parallel with the first diode. The control circuit drives the inductor load by applying a control voltage to the first switch before applying a first ON-voltage to the second switch. The first ON-voltage turns ON the second switch. The control voltage is greater than zero and less than a second ON-voltage. The second ON-voltage turns ON the first switch. The control voltage causes the first switch to operate in weak inversion.
摘要翻译：用于驱动连接到与直流电压源串联连接的第一和第二开关之间的节点的感性负载的驱动控制器包括第一二极管，第二二极管的串联电路和电感器以及控制电路。第一二极管是第一开关的寄生二极管，并与第一开关反并联。串联电路与第一二极管并联连接。控制电路通过在向第二开关施加第一导通电压之前向第一开关施加控制电压来驱动电感器负载。第一个接通电压接通第二个开关。控制电压大于零且小于第二导通电压。第二个接通电压打开第一个开关。控制电压使第一个开关在弱反转下工作。

10. 发明授权

US08890496B2 Drive controller 有权
标题翻译：驱动控制器
公开(公告)号：US08890496B2
公开(公告)日：2014-11-18
申请号：US13191765
申请日：2011-07-27
申请人： Takeshi Inoue , Masakiyo Sumitomo
发明人： Takeshi Inoue , Masakiyo Sumitomo
IPC分类号： G05F1/00 , H02M3/158 , H02M3/155
CPC分类号： H02M3/158 , H01L2224/05554 , H01L2224/0603 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/19107 , H02M2003/1555 , H01L2924/00 , H01L2924/00012
摘要： A drive controller for driving an inductive load connected to a node between first and second switches connected in series with a direct current voltage source includes a first diode, a series circuit of a second diode and an inductor, and a control circuit. The first diode is a parasitic diode of the first switch and connected in antiparallel with the first switch. The series circuit is connected in parallel with the first diode. The control circuit drives the inductor load by applying a control voltage to the first switch before applying a first ON-voltage to the second switch. The first ON-voltage turns ON the second switch. The control voltage is greater than zero and less than a second ON-voltage. The second ON-voltage turns ON the first switch. The control voltage causes the first switch to operate in weak inversion.
摘要翻译：用于驱动连接到与直流电压源串联连接的第一和第二开关之间的节点的感性负载的驱动控制器包括第一二极管，第二二极管的串联电路和电感器以及控制电路。第一二极管是第一开关的寄生二极管，并与第一开关反并联。串联电路与第一二极管并联连接。控制电路通过在向第二开关施加第一导通电压之前向第一开关施加控制电压来驱动电感器负载。第一个接通电压接通第二个开关。控制电压大于零且小于第二导通电压。第二个接通电压打开第一个开关。控制电压使第一个开关在弱反转下工作。

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