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1. 发明授权

US06327654B1 Semiconductor integrated circuit for cryptographic process and encryption algorithm alternating method 失效
标题翻译：半导体集成电路用于加密处理和加密算法的交替方法
公开(公告)号：US06327654B1
公开(公告)日：2001-12-04
申请号：US09151774
申请日：1998-09-11
申请人： Yukihito Oowaki , Hiroshige Fujii , Hideo Shimizu , Takehisa Kato , Naoki Endo , Atsushi Masuda , Hiroaki Nishi , Kazunori Ohuchi , Masatoshi Sekine
发明人： Yukihito Oowaki , Hiroshige Fujii , Hideo Shimizu , Takehisa Kato , Naoki Endo , Atsushi Masuda , Hiroaki Nishi , Kazunori Ohuchi , Masatoshi Sekine
IPC分类号： G06F1130
CPC分类号： G06F21/72 , H04L9/0625 , H04L2209/08 , H04L2209/122 , H04L2209/125
摘要： A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.
摘要翻译：根据本发明的用于密码处理的半导体集成电路包括：随机化单元，用于基于配置信息随机化作为输入数据的两个分割部分之一的第一输入数据，以识别随机化过程中的算法;函数F部分，用于接收已经经过随机化处理然后对数据进行编码处理的数据，以及用于接收作为输入数据的两个分割部分中的另外两个部分的第二输入数据和来自功能F部分的输出数据的异或逻辑和电路，输出第二输入数据和输出数据的异或逻辑和。

2. 发明授权

US06349395B2 Configurable integrated circuit and method of testing the same 失效
标题翻译：可配置的集成电路和测试方法相同
公开(公告)号：US06349395B2
公开(公告)日：2002-02-19
申请号：US09154027
申请日：1998-09-16
申请人： Kazunori Ohuchi , Masako Yoshida , Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
发明人： Kazunori Ohuchi , Masako Yoshida , Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
IPC分类号： G01R3128
CPC分类号： G01R31/318516
摘要： An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.
摘要翻译：集成电路具有可配置逻辑块，其是可重新配置的，执行固定操作的硬连线逻辑块，以及存储器。存储器存储用于配置可配置逻辑块的配置数据，用于确定可配置逻辑块和硬连线逻辑块之间的连接的块连接数据，以及用于确定部分电路之间的连接的部分电路连接数据，每个部分电路由选择的逻辑块组成在可配置和硬连线的逻辑块之间。这些数据由逻辑块共享，以减少集成电路中的存储器数量并提高集成电路的封装密度。

3. 发明授权

US6112163A Semiconductor integrated circuit and test method therefor 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US6112163A
公开(公告)日：2000-08-29
申请号：US38373
申请日：1998-03-11
申请人： Yukihito Oowaki , Masatoshi Sekine , Hiroshige Fujii
发明人： Yukihito Oowaki , Masatoshi Sekine , Hiroshige Fujii
IPC分类号： G01R31/317 , G01R31/3185 , G06F11/22 , G01R15/12
CPC分类号： G01R31/318566
摘要： A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.
摘要翻译：可重构电路被重建为三个或更多个操作电路块。在测试时，将相同的数据输入到每个重建的操作电路块。形成在可重构电路中的多数电路比较了操作电路块的操作结果并输出指示哪些操作电路块处于故障状态的信息。

4. 发明授权

US6026480A Processor having bug avoidance function and method for avoiding bug in processor 失效
标题翻译：处理器具有避免错误的功能和方法，以避免处理器中的错误
公开(公告)号：US6026480A
公开(公告)日：2000-02-15
申请号：US37067
申请日：1998-03-09
申请人： Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
发明人： Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
IPC分类号： G06F11/28 , G06F9/30 , G06F9/318 , G06F9/38 , G06F11/00 , G06F11/20 , G06F11/22 , G06F15/78 , G06F9/28
CPC分类号： G06F9/328 , G06F11/004 , G06F11/20 , G06F9/30181 , G06F9/30196 , G06F9/3861
摘要： A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.
摘要翻译：一种可重新配置电路，其中提供其指令或其解码结果和所述寄存器文件的输出的部分或全部，并且其电路结构可以通过外部信号改变。如果当部分或全部指令或其解码结果和寄存器文件的输出满足特定条件时发生错误，则可通过外部信号重建可重构电路，以便在该特定条件下输出第一信号。中断控制电路控制处理单元，以便基于第一信号或处理进行处理，以便在输入第一信号时避免错误。

5. 发明授权

US6157997A Processor and information processing apparatus with a reconfigurable circuit 失效
标题翻译：具有外部提供的可重构电路的处理器通过将数据写入预定义的存储器地址而被激活
公开(公告)号：US6157997A
公开(公告)日：2000-12-05
申请号：US38834
申请日：1998-03-12
申请人： Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
发明人： Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
IPC分类号： G06F7/00 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3822 , G06F15/7867 , G06F9/30181 , G06F9/30196 , G06F9/3897
摘要： Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted. When the particular instruction is executed, the first reconfigurable circuit outputs a control signal and the second reconfigurable circuit executes the predetermined operating function by that control signal.
摘要翻译：指令解码器的一部分或全部由第一可重构电路构成，其中其电路结构可以根据外部信号而改变。此外，预先提供连接到作为处理单元的一部分的寄存器堆的输出侧并且其中其电路结构可以根据外部信号改变的第二可重新配置电路。为了特别使用，为了实现预定的操作功能，第二可重构电路由外部信号重建。此外，设置与预定操作功能相对应的特定指令，并且通过外部信号重构第一可重新配置电路，当输入特定指令时，输出相应的控制信号。当执行特定指令时，第一可重新配置电路输出控制信号，第二可重新配置电路通过该控制信号执行预定的操作功能。

6. 发明授权

US5933380A Semiconductor memory device having a multilayered bitline structure with respective wiring layers for reading and writing data 失效
标题翻译：具有多层位线结构的半导体存储器件，具有用于读取和写入数据的各个布线层
公开(公告)号：US5933380A
公开(公告)日：1999-08-03
申请号：US871587
申请日：1997-06-09
申请人： Kenji Tsuchida , Yukihito Oowaki , Kazunori Ohuchi
发明人： Kenji Tsuchida , Yukihito Oowaki , Kazunori Ohuchi
IPC分类号： H01L21/8242 , G11C7/18 , G11C11/401 , H01L27/108 , G11C7/02
CPC分类号： G11C7/18
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.
摘要翻译：半导体存储器件包括具有多个存储单元的存储单元阵列，该存储单元阵列被划分为多个块，多个第一位线布置在每个块中，多个第一位线形成多个第一位线所述多个第二位线具有折叠的位线结构，其中所述多个第一位线中的两个作为基本单元，多个第二位线被布置成对应于所述块中的至少一个并且形成在所述第一位线上方，所述多个第二位线形成多个第二位线对，其具有折叠的位线结构，其中所述多个第二位线中的两个作为基本单元;多个读出放大器电路，被布置为对应于所述多个第二位线对，用于检测和放大存储在所述存储器单元中的信息以及多个选择电路，用于选择包括在所述多个第一位线对之一中的两个第一位线之一至s 选择性地将所选择的第一位线与包括在所述多个第二位线对之一中的第二位线之一中的一个位线连接。

7. 发明申请

US20060271799A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20060271799A1
公开(公告)日：2006-11-30
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压。

8. 发明授权

US07057917B2 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor 失效
标题翻译：具有耦合到电容器的本征存取晶体管的铁电存储器
公开(公告)号：US07057917B2
公开(公告)日：2006-06-06
申请号：US10743906
申请日：2003-12-24
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

9. 发明授权

US06643162B2 Ferroelectric memory having a device responsive to current lowering 有权
标题翻译：铁电存储器具有响应于电流降低的装置
公开(公告)号：US06643162B2
公开(公告)日：2003-11-04
申请号：US09799694
申请日：2001-03-07
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.
摘要翻译：铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压，升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

10. 发明授权

US06545323B2 Semiconductor memory device including a pair of MOS transistors forming a detection circuit 失效
标题翻译：半导体存储器件包括形成检测电路的一对MOS晶体管
公开(公告)号：US06545323B2
公开(公告)日：2003-04-08
申请号：US10014662
申请日：2001-12-14
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L2976
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
摘要翻译：半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

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