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1. 发明授权

US06363010B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06363010B1
公开(公告)日：2002-03-26
申请号：US09899290
申请日：2001-07-06
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

2. 发明授权

US06198687B1 Semiconductor memory device having a plurality of transfer gates and improved word line and column select timing for high speed write operations 失效
标题翻译：具有多个传输门的半导体存储器件和用于高速写入操作的改进的字线和列选择定时
公开(公告)号：US06198687B1
公开(公告)日：2001-03-06
申请号：US08716884
申请日：1996-09-20
申请人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
发明人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
IPC分类号： G11C11407
CPC分类号： G11C8/18
摘要： A semiconductor memory device which receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from an external device. The device includes rewritable memory cells formed on a semiconductor substrate, a plurality of bit lines, a plurality of word lines, and a transfer gate coupled between the bit lines and input/output (I/O) lines and controlled by a column select line or signal. In one embodiment, a first transfer gate is connected between the bit lines and a second transfer gate, the second transfer gate connected between the first transfer gate and an input/output (I/O) line and controlled by a column select line (CSL). A third transfer gate may also by provided. The first transfer gate is driven in response to a clock signal which is enabled at substantially the same time as a word line of the plurality of word lines is selected during both read and write cycles. Thus, during a write cycle in which the CAS signal is enabled prior to the RAS signal, a selected CSL can be increased from a first voltage (VSS) to one of a second voltage (Vdd) and {fraction (3/2)} Vdd as soon as a column address is input.
摘要翻译：从外部设备接收行地址选通（RAS）信号和列地址选通（CAS）信号的半导体存储器件。该器件包括形成在半导体衬底上的可重写存储单元，多个位线，多个字线和耦合在位线和输入/输出（I / O）线之间并由列选择线控制的传输栅极或信号。在一个实施例中，第一传输门连接在位线和第二传输门之间，第二传输门连接在第一传输门和输入/输出（I / O）线之间，并由列选择线（CSL ）。也可以通过提供第三传输门。响应于在读取和写入周期期间选择多个字线的字线的基本上相同的时间使能的时钟信号来驱动第一传输门。因此，在RAS信号之前的CAS信号被使能的写周期中，所选择的CSL可以从第一电压（VSS）增加到第二电压（Vdd）和{分数（3/2）}之一一旦列地址被输入，就会Vdd。

3. 发明授权

US5602789A Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller 失效
标题翻译：具有写入验证控制器的电可擦除和可编程的非易失性和多级存储器系统
公开(公告)号：US5602789A
公开(公告)日：1997-02-11
申请号：US518024
申请日：1995-08-22
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3413 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
摘要翻译：用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

4. 发明授权

US4611237A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4611237A
公开(公告)日：1986-09-09
申请号：US635474
申请日：1984-07-30
申请人： Kazunori Ohuchi , Mitsugi Ogura , Kenji Natori
发明人： Kazunori Ohuchi , Mitsugi Ogura , Kenji Natori
IPC分类号： H01L29/78 , H01L21/82 , H01L23/522 , H01L23/535 , H01L29/41 , H01L29/417
CPC分类号： H01L23/522 , H01L23/535 , H01L29/41725 , H01L2924/0002
摘要： A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.
摘要翻译： MOS晶体管集成电路器件具有与MOS晶体管的源区和漏极区交叉的至少一个互连层，使得它覆盖在这些源极和漏极区上。在MOS晶体管的源区和漏区中的至少一个的表面上形成导电层。导电层在其间具有绝缘层与互连层交叉，使得其位于互连层下面。导电层与源极和漏极引出电极分离并与互连层电绝缘。

5. 发明授权

US06545909B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06545909B2
公开(公告)日：2003-04-08
申请号：US10094215
申请日：2002-03-11
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.
摘要翻译：存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。位线连接位线控制器和存储单元。在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

6. 发明授权

US6044013A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6044013A
公开(公告)日：2000-03-28
申请号：US314446
申请日：1999-05-19
申请人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
发明人： Tomoharu Tanaka , Kazunori Ohuchi , Toru Tanzawa , Ken Takeuchi
IPC分类号： G11C7/10 , G11C7/12 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C7/1006 , G11C7/1078 , G11C7/12 , G11C2211/5621 , G11C2211/5642
摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.
摘要翻译：提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

7. 发明授权

US5933436A Error correction/detection circuit and semiconductor memory device using the same 失效
标题翻译：误差校正/检测电路及使用其的半导体存储器件
公开(公告)号：US5933436A
公开(公告)日：1999-08-03
申请号：US611818
申请日：1996-03-06
申请人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
发明人： Toru Tanzawa , Tomoharu Tanaka , Riichiro Shirota , Kazunori Ohuchi
IPC分类号： G06F12/16 , G06F11/10 , H03M13/15 , G11C29/00
CPC分类号： G06F11/1008 , H03M13/151
摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.
摘要翻译：一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据。

8. 发明授权

US5386422A Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
公开(公告)号：US5386422A
公开(公告)日：1995-01-31
申请号：US229761
申请日：1994-04-19
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3404 , G11C16/3413 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

9. 发明授权

US4947088A Method and apparatus for controlling reel tension 失效
标题翻译：用于控制卷轴张力的方法和装置
公开(公告)号：US4947088A
公开(公告)日：1990-08-07
申请号：US143807
申请日：1988-01-14
申请人： Toshiro Kisakibaru , Tsuguo Gotoh , Kazunori Ohuchi
发明人： Toshiro Kisakibaru , Tsuguo Gotoh , Kazunori Ohuchi
IPC分类号： H02P27/06 , B65H23/195 , B65H23/198 , B65H59/38 , H02P7/298
CPC分类号： B65H23/1955
摘要： Hitherto, in the tension control for a reel, it is impossible to exceed the tension controlling range of about 1:10 which is determined by the tension controlling range of a single DC motor, so that for the reel which requires a tension controlling range over 1:10, a plurality of DC motors have been combined and used or a gear ratio between the reel and the DC motor has been changed for many years so far.In this invention an attention is paid to the fact such that the unpreferable phenomena such as a change in characteristic due to an armature reaction, and deterioration of rectification or the like which are caused by setting the field system to a low level can be fairly suppressed by limiting the setting and controlling range to a low region of an armature current. The field system is set to a low level so that a ratio of a field magnetic flux to a diameter of a coil becomes a value lower than the maximum value and also the upper limit of an operating armature current which is practically applied is set to be low, thereby making it possible to perform the stable tension control within a low tension range which could not be realized so far by a single DC motor.

10. 发明授权

US4926382A Divided bit line type dynamic random access memory with charging/discharging current suppressor 失效
标题翻译：具有充电/放电电流抑制器的分立位线型动态随机存取存储器
公开(公告)号：US4926382A
公开(公告)日：1990-05-15
申请号：US275395
申请日：1988-11-23
申请人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
发明人： Koji Sakui , Kazunori Ohuchi , Fujio Masuoka
IPC分类号： G11C11/401 , G11C11/4097
CPC分类号： G11C11/4097
摘要： A divided bit line type dynamic semiconductor memory device comprises parallel main bit line pairs, divided bit line pairs provided at each main bit line pair, parallel word lines insulatively crossing the divided bit line pairs, and memory cells provided at the cross points between the divided bit line pairs and the word lines. First sense amplifiers are coupled to the divided bit line pairs. Second sense amplifiers are coupled to the main bit line pairs. First transfer gate sections are coupled between the divided bit line pairs and the main bit line pairs, respectively. Second transfer gate sections are coupled between the main bit line pairs and the second sense amplifier circuits, respectively. A charging/discharging current suppressor is provided which, in both of the read and restoring modes, restricts the amplitude of the potential change, due to charging/discharging, of a specifi main bit line pair associated with a selected divided bit line pair including a selected cell to be smaller than a full potential change defined by the source voltage and ground potential of the device, whereby a charging/discharging cuffent flowing through the specific main bit line pair is reduced so that the dissipation power of the dRAM is saved and its operation speed is improved.
摘要翻译：分割位线型动态半导体存储器件包括并行主位线对，在每个主位线对上设置的分开的位线对，与划分的位线对绝对地交叉的并行字线，以及设置在分割的位线对之间的交叉点处的存储单元位线对和字线。第一读出放大器耦合到分开的位线对。第二读出放大器耦合到主位线对。第一传输门部分分别耦合在分开的位线对和主位线对之间。第二传输门部分分别耦合在主位线对和第二读出放大器电路之间。提供了一种充电/放电电流抑制器，其在读取和恢复模式中都限制与所选择的分割位线对相关联的特定位线对的由于充电/放电引起的电位变化的幅度，包括所选择的电池小于由器件的源极电压和接地电位限定的全部电位变化，从而减小流过特定主位线对的充电/放电脉冲，从而节省dRAM的耗散功率，操作速度提高。

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