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1. 发明授权

US06906944B2 Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US06906944B2
公开(公告)日：2005-06-14
申请号：US10676004
申请日：2003-10-02
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C14/00 , G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.
摘要翻译：铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压，升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

2. 发明授权

US06366490B1 Semiconductor memory device using ferroelectric film 有权
标题翻译：使用铁电薄膜的半导体存储器件
公开(公告)号：US06366490B1
公开(公告)日：2002-04-02
申请号：US09879054
申请日：2001-06-13
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： This invention is such that, in a series-connected TC parallel-unit type ferroelectric RAM composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor is connected between the source and drain of a cell transistor, for instance, plate electrode wires are provided in the longitudinal direction of bit line pairs. The plate electrode wires are shared in memory block groups, each group being a set of a plurality of memory cell blocks connected to the same bit line pair. This causes only the memory cells read from or written into to be accessed by the selected word line and selected plate electrode wire in one select operation.
摘要翻译：本发明使得在由多个单元电池的串联连接构成的串联连接的TC并联单元型铁电RAM中，每个单电池使得在单电池晶体管的源极和漏极之间连接有铁电电容器例如，在位线对的长度方向上设置平板电极线。板电极线在存储块组中共享，每组是连接到同一位线对的多个存储单元块的集合。这将导致在一个选择操作中，所选择的字线和选定的板电极线只能读取或写入存储单元。

3. 发明授权

US07057917B2 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor 失效
标题翻译：具有耦合到电容器的本征存取晶体管的铁电存储器
公开(公告)号：US07057917B2
公开(公告)日：2006-06-06
申请号：US10743906
申请日：2003-12-24
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

4. 发明授权

US06643162B2 Ferroelectric memory having a device responsive to current lowering 有权
标题翻译：铁电存储器具有响应于电流降低的装置
公开(公告)号：US06643162B2
公开(公告)日：2003-11-04
申请号：US09799694
申请日：2001-03-07
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.
摘要翻译：铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压，升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

5. 发明申请

US20080285327A1 Ferroelectric Memory and Semiconductor Memory 审中-公开
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20080285327A1
公开(公告)日：2008-11-20
申请号：US11934399
申请日：2007-11-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22 , G11C11/401
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

6. 发明授权

US06671200B2 Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit 有权
标题翻译：铁电随机存取存储器，其隔离晶体管耦合在读出放大器和均衡电路之间
公开(公告)号：US06671200B2
公开(公告)日：2003-12-30
申请号：US10372886
申请日：2003-02-26
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

7. 发明授权

US07295456B2 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor 有权
标题翻译：具有与铁电电容器并联连接的本征晶体管的链式铁电随机存取存储器（CFRAM）
公开(公告)号：US07295456B2
公开(公告)日：2007-11-13
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

8. 发明授权

US06483737B2 Ferroelectric memory device 有权
公开(公告)号：US06483737B2
公开(公告)日：2002-11-19
申请号：US09956938
申请日：2001-09-21
申请人： Yoshiaki Takeuchi , Sumiko Doumae , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Sumiko Doumae , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric memory device comprises a word line, first and second bit lines cross to the word line, a memory cell including a first transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the first bit line, a second transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the second bit line, and a ferroelectric cell capacitor coupled to the other of source and drain of the first and second transistor, and first and second capacitors each coupled via a switching transistor to a respective one of the first and second bit lines, wherein first and second voltages complementary to each other are applied to the first and second bit lines, via the first and second capacitors, respectively.

9. 发明申请

US20060193162A1 Ferroelectric Memory and Semiconductor Memory 有权
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20060193162A1
公开(公告)日：2006-08-31
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

10. 发明授权

US06552922B2 Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair 有权
标题翻译：具有耦合在读出放大器和位线对之间的重写晶体管的链式铁电随机存取存储器（FRAM）
公开(公告)号：US06552922B2
公开(公告)日：2003-04-22
申请号：US10228067
申请日：2002-08-27
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

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