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1. 发明授权

US06349395B2 Configurable integrated circuit and method of testing the same 失效
标题翻译：可配置的集成电路和测试方法相同
公开(公告)号：US06349395B2
公开(公告)日：2002-02-19
申请号：US09154027
申请日：1998-09-16
申请人： Kazunori Ohuchi , Masako Yoshida , Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
发明人： Kazunori Ohuchi , Masako Yoshida , Yukihito Oowaki , Hiroshige Fujii , Masatoshi Sekine
IPC分类号： G01R3128
CPC分类号： G01R31/318516
摘要： An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.
摘要翻译：集成电路具有可配置逻辑块，其是可重新配置的，执行固定操作的硬连线逻辑块，以及存储器。存储器存储用于配置可配置逻辑块的配置数据，用于确定可配置逻辑块和硬连线逻辑块之间的连接的块连接数据，以及用于确定部分电路之间的连接的部分电路连接数据，每个部分电路由选择的逻辑块组成在可配置和硬连线的逻辑块之间。这些数据由逻辑块共享，以减少集成电路中的存储器数量并提高集成电路的封装密度。

2. 发明授权

US06545323B2 Semiconductor memory device including a pair of MOS transistors forming a detection circuit 失效
标题翻译：半导体存储器件包括形成检测电路的一对MOS晶体管
公开(公告)号：US06545323B2
公开(公告)日：2003-04-08
申请号：US10014662
申请日：2001-12-14
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L2976
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
摘要翻译：半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

3. 发明授权

US5895956A Semiconductor memory device 失效
公开(公告)号：US5895956A
公开(公告)日：1999-04-20
申请号：US569844
申请日：1995-12-08
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L21/8242 , G11C11/4091 , H01L27/108 , H01L27/12 , H01L29/76 , H01L29/786 , H01L27/01
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

4. 发明授权

US5717625A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5717625A
公开(公告)日：1998-02-10
申请号：US784963
申请日：1997-01-16
申请人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
发明人： Takehiro Hasegawa , Yukihito Oowaki , Shigeyoshi Watanabe , Ken-ichi Maeda , Mitsuo Saito , Masako Yoshida , Ryo Fukuda , Shinichiro Shiratake
IPC分类号： G11C8/08 , G11C11/404 , G11C15/00
CPC分类号： G11C8/08 , G11C11/4045
摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.
摘要翻译：在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

5. 发明授权

US06342408B1 Method of manufacturing semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US06342408B1
公开(公告)日：2002-01-29
申请号：US09658573
申请日：2000-09-08
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L21336
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.
摘要翻译：半导体器件包括用作形成在绝缘膜上的衬底的半导体层，布置在半导体层上并且各自具有栅极，源极和漏极的多个MOS晶体管，多个MOS的一对MOS晶体管构成检测电路的晶体管，用于检测施加到栅极的电位的大小，作为一对晶体管的电导率差，以及与半导体层的导电类型相同的导电类型的扩散层区域，布置在源的一部分以及构成检测电路的一对MOS晶体管的漏极，用于将用作一对MOS晶体管的基板的部分彼此连接。

6. 发明授权

US6130461A Semiconductor memory device 失效
公开(公告)号：US6130461A
公开(公告)日：2000-10-10
申请号：US291042
申请日：1999-04-14
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L21/8242 , G11C11/4091 , H01L27/108 , H01L27/12 , H01L29/76 , H01L29/786
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

7. 发明授权

US5661678A Semiconductor memory device using dynamic type memory cells 失效
标题翻译：半导体存储器件采用动态型存储单元
公开(公告)号：US5661678A
公开(公告)日：1997-08-26
申请号：US570966
申请日：1995-12-12
申请人： Masako Yoshida , Yukihito Oowaki , Takehiro Hasegawa , Kiyofumi Ochii , Masayuki Koizumi
发明人： Masako Yoshida , Yukihito Oowaki , Takehiro Hasegawa , Kiyofumi Ochii , Masayuki Koizumi
IPC分类号： H01L21/8242 , G11C11/404 , G11C11/405 , H01L27/108 , G11C7/00
CPC分类号： G11C11/404 , H01L27/108 , H01L27/10808 , H01L27/10829
摘要： A semiconductor memory device comprises a memory cell array including NAND type memory cell units arranged in matrix and having a plurality of dynamic type memory cells connected in series, a plurality of word lines, a plurality of bit lines arranged within the memory cell array, the plurality of bit lines including a bit line pairs which are arranged adjacent to each other or between which at least one bit line is interposed, and a plurality of sense amplifiers of a folded bit line type, provided in each of the plurality of bit line pairs, in which the memory cells are provided in positions corresponding to intersections of the bit lines and the word lines, and complementary data are written to two memory cells connected to each of the plurality of bit line pairs and one word line, and the two memory cells store one-bit data.
摘要翻译：半导体存储器件包括存储单元阵列，其包括以矩阵形式布置的NAND型存储单元单元，并且具有串联连接的多个动态型存储单元，多个字线，布置在存储单元阵列内的多个位线，多个位线包括彼此相邻布置或位于其中的至少一个位线之间布置的位线对以及设置在多个位线对中的每一个中的折叠位线类型的多个读出放大器其中存储单元被提供在与位线和字线的交点对应的位置中，并且互补数据被写入连接到多个位线对和一个字线中的每一个的两个存储器单元，并且两个存储器单元存储一位数据。

8. 发明授权

US06677797B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06677797B2
公开(公告)日：2004-01-13
申请号：US10023947
申请日：2001-12-21
申请人： Atsushi Kameyama , Tsuneaki Fuse , Masako Yoshida , Kazunori Ohuchi
发明人： Atsushi Kameyama , Tsuneaki Fuse , Masako Yoshida , Kazunori Ohuchi
IPC分类号： H03L500
CPC分类号： H03K19/0016
摘要： An integrated circuit has first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a high threshold value, while the second logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a low threshold value. An output switch circuit intervenes between the p-type FET and n-type FET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.
摘要翻译：集成电路具有第一和第二逻辑电路，其具有公共的输入端和相同的互补逻辑功能。第一逻辑电路具有每个具有高阈值的p型FET电路块和n型FET电路块，而第二逻辑电路具有p型FET电路块和n型FET电路块，每个具有低阈值。输出开关电路插入每个逻辑电路中的p型FET和n型FET电路块之间，并且控制到每个逻辑电路的电源连接。在操作中，第二逻辑电路的输出连接到输出端以实现低功耗。在待机状态下，第一逻辑电路的输出连接到输出端子以实现低泄漏电流。

9. 发明授权

US06466054B2 Level converter circuit 失效
标题翻译：电平转换电路
公开(公告)号：US06466054B2
公开(公告)日：2002-10-15
申请号：US09811699
申请日：2001-03-20
申请人： Atsushi Kameyama , Tsuneaki Fuse , Kazunori Ohuchi , Masako Yoshida
发明人： Atsushi Kameyama , Tsuneaki Fuse , Kazunori Ohuchi , Masako Yoshida
IPC分类号： H03K190175
CPC分类号： H03K19/018521
摘要： A level converter circuit includes two p-channel MOSFETs and two n-channel MOSFETs of gate-grounded type which receive complementary signals from a logic circuit, p-channel cross-coupled FETs, and n-channel cross-coupled FETs. The two FETs constructing each cross-coupled FETs can be driven by complementary inputs by supplying an output of the logic circuit operated on a low voltage and a logically inverted output thereof to each cross-coupled FETs via the gate-grounded FETs, and as a result, the gain characteristic of the cross-coupled FETs can be enhanced. The level converter circuit with low power consumption which has large tolerance for the element characteristic and converts a logic level which is as low as approximately 0.5V to approximately 1V to 3V which is a normal logic level.
摘要翻译：电平转换器电路包括两个p沟道MOSFET和栅极接地型的两个n沟道MOSFET，其接收来自逻辑电路，p沟道交叉耦合FET和n沟道交叉耦合FET的互补信号。构成每个交叉耦合FET的两个FET可以通过互补输入来驱动，该逻辑电路通过栅极接地的FET将低电压和逻辑反相输出的输出提供给每个交叉耦合的FET，并且作为结果，可以提高交叉耦合FET的增益特性。具有低功耗的电平转换器电路，其具有对元件特性的较大容差，并将低至约0.5V至大约1V至3V的逻辑电平转换为大约1V至3V，这是正常逻辑电平。

10. 发明申请

US20100280083A1 NOVEL CATECHOL DERIVATIVE, PHARMACEUTICAL COMPOSITION CONTAINING THE SAME, USE OF THE CATECHOL DERIVATIVE, AND USE OF THE PHARMACEUTICAL COMPOSITION 有权
标题翻译：新CATECHOL衍生物，含有该药物的药物组合物，CATECHOL衍生物的使用和药物组合物的使用
公开(公告)号：US20100280083A1
公开(公告)日：2010-11-04
申请号：US12810275
申请日：2008-12-22
申请人： Takehiro Ishikawa , Hitoshi Inoue , Satoko Kobayashi , Masako Yoshida , Hiroaki Shiohara , Yasunori Ueno , Nobuyuki Tanaka
发明人： Takehiro Ishikawa , Hitoshi Inoue , Satoko Kobayashi , Masako Yoshida , Hiroaki Shiohara , Yasunori Ueno , Nobuyuki Tanaka
IPC分类号： A61K31/4245 , C07D271/06 , C07D413/04 , C07D417/10 , A61K31/427 , A61P25/16
CPC分类号： C07D271/06 , C07D413/04 , C07D413/10 , C07D417/10
摘要： The present invention provides compounds represented by general formula (I): or pharmaceutical acceptable salts thereof, wherein R1 and R2 are each hydrogen, lower acyl, lower alkoxycarbonyl or the like; R3 is halo-lower alkyl, lower acyl, halo-lower alkylcarbonyl, cycloalkylcarbonyl, optionally substituted arylcarbonyl, lower alkoxycarbonyl or the like; R4 is lower alkyl, halo-lower alkyl, cycloalkyl, lower alkoxy-lower alkyl or the like, which exhibit potent COMT inhibitory activities. The present invention also provides pharmaceutical compositions containing said compound, and uses thereof.
摘要翻译：本发明提供由通式（I）表示的化合物或其药学上可接受的盐，其中R 1和R 2各自为氢，低级酰基，低级烷氧基羰基等; 低级酰基，卤代低级烷基羰基，环烷基羰基，任意取代的芳基羰基，低级烷氧基羰基等; R4是表现出强大的COMT抑制活性的低级烷基，卤代低级烷基，环烷基，低级烷氧基 - 低级烷基等。本发明还提供含有所述化合物的药物组合物及其用途。

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